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參數(shù)資料
| 型號： | CY7C68001 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller |
| 中文描述： | EZ - USB FX2的USB微控制器的高速USB外設控制器 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 1588K |
| 代理商： | CY7C68001 |
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CY7C68001
Document #: 38-08013 Rev. *H
Page 5 of 42
3.6.3
Endpoint Configurations (High-speed Mode)
Endpoint 0 is the same for every configuration as it serves as
the CONTROL endpoint. For Endpoints 2, 4, 6, and 8, refer to
Figure 3-1
. Endpoints 2, 4, 6, and 8 may be configured by
choosing either:
One configuration from Group A and one from Group B
One configuration from Group C.
Some example endpoint configurations are as follows.
EP2: 1024 bytes double-buffered, EP6: 512 bytes quad-
buffered.
EP2: 512 bytes double-buffered, EP4: 512 bytes double-
buffered, EP6: 512 bytes double-buffered, EP8: 512 bytes
double buffered.
EP2: 1024 bytes quad-buffered.
3.6.4
At power-on-reset, the endpoint memories are configured as
follows:
EP2: Bulk OUT, 512 bytes/packet, 2x buffered.
EP4: Bulk OUT, 512 bytes/packet, 2x buffered.
EP6: Bulk IN, 512 bytes/packet, 2x buffered.
EP8: Bulk IN, 512 bytes/packet, 2x buffered.
Default Endpoint Memory Configuration
3.7
The
SX2
presents two interfaces to the external master.
1. A FIFO interface through which EP2, 4, 6, and 8 data flows.
2. A command interface, which is used to set up the
SX2
, read
status, load descriptors, and access Endpoint 0.
External Interface
3.7.1
The
SX2
slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories and
Architecture
are controlled by FIFO control signals (IFCLK, CS#, SLRD,
SLWR, SLOE, PKTEND, and FIFOADR[2:0]).
The
SX2
command interface is used to set up the
SX2
, read
status, load descriptors, and access Endpoint 0. The
command interface has its own READY signal for gating
writes, and an INT# signal to indicate that the
SX2
has data to
be read, or that an interrupt event has occurred. The command
interface uses the same control signals (IFCLK, CS#, SLRD,
SLWR, SLOE, and FIFOADR[2:0]) as the FIFO interface,
except for PKTEND.
3.7.2
Control Signals
3.7.2.1
The
SX2
has three address pins that are used to select either
the FIFOs or the command interface. The addresses corre-
spond to the following table.
FIFOADDR Lines
The
SX2
accepts either an internally derived clock (30 or 48
MHz) or externally supplied clock (IFCLK, 5–50 MHz), and
SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals
from an external master. The interface can be selected for 8-
512
512
512
512
EP6
EP8
512
512
512
512
EP6
512
512
512
512
EP2
512
512
EP6
1024
1024
EP6
1024
1024
EP2
1024
1024
1024
EP2
1024
1024
512
512
EP8
EP0 IN&OUT
64
64
64
64
64
64
512
512
EP8
Group A
Group C
512
512
512
512
EP2
EP4
512
512
512
512
EP2
1024
1024
EP2
Group B
Figure 3-1. Endpoint Configuration
Table 3-3. FIFO Address Lines Setting
Address/Selection
FIFO2
FIFO4
FIFO6
FIFO8
COMMAND
RESERVED
RESERVED
RESERVED
FIFOADR2 FIFOADR1 FIFOADR0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
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