參數(shù)資料
型號： CY7C68001
廠商： Cypress Semiconductor Corp.
元件分類： 基準電壓源/電流源
英文描述： EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller
中文描述： EZ - USB FX2的USB微控制器的高速USB外設(shè)控制器
文件頁數(shù)： 12/42頁
文件大?。?/td> 1588K
代理商： CY7C68001
CY7C68001
Document #: 38-08013 Rev. *H
Page 12 of 42
6.3
CY7C68001 Pin Definitions
Table 6-1.
SX2
Pin Definitions
QFN
Pin
Pin
3
10
6
13
9
16
DMINUS
8
15
42
49
RESET#
SSOP
Name
AVCC
AGND
Type
Power
Power
I/O/Z
I/O/Z
Input
Default
N/A
N/A
Z
Z
N/A
Description
Analog V
CC
. This signal provides power to the analog section of the chip.
Analog Ground
. Connect to ground with as short a path as possible.
USB D– Signal
. Connect to the USB D– signal.
USB D+ Signal
. Connect to the USB D+ signal.
Active LOW Reset
. Resets the entire chip. This pin is normally tied to V
CC
through a 100K resistor, and to GND through a 0.1-
μ
F capacitor.
Crystal Input
. Connect this signal to a 24-MHz parallel-resonant, fundamental
mode crystal and 20-pF capacitor to GND. It is also correct to drive XTALIN with
an external 24-MHz square wave derived from another clock source.
Crystal Output
. Connect this signal to a 24-MHz parallel-resonant, fundamental
mode crystal and 20-pF capacitor to GND. If an external clock is used to drive
XTALIN, leave this pin open.
No Connect
.
This pin must be left unconnected.
DPLUS
5
12
XTALIN
Input
N/A
4
11
XTALOUT
Output
N/A
54
5
NC
Output
O
33
40
READY
Output
L
READY
is an output-only ready that gates external command reads and writes.
Active High.
INT#
is an output-only external interrupt signal. Active Low.
SLOE
is an input-only output enable with programmable polarity (POLAR.4) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
FIFOADR2
is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
FIFOADR0
is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
FIFOADR1
is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
PKTEND
is an input-only packet end with programmable polarity (POLAR.5) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
FLAGD
is a programmable slave-FIFO output status flag signal. CS# is a master
chip select (default).
FD[0]
is the bidirectional FIFO/Command data bus.
FD[1]
is the bidirectional FIFO/Command data bus.
FD[2]
is the bidirectional FIFO/Command data bus.
FD[3]
is the bidirectional FIFO/Command data bus.
FD[4]
is the bidirectional FIFO/Command data bus.
FD[5]
is the bidirectional FIFO/Command data bus.
FD[6]
is the bidirectional FIFO/Command data bus.
FD[7]
is the bidirectional FIFO/Command data bus.
FD[8]
is the bidirectional FIFO data bus.
FD[9]
is the bidirectional FIFO data bus.
FD[10]
is the bidirectional FIFO data bus.
FD[11]
is the bidirectional FIFO data bus.
FD[12]
is the bidirectional FIFO data bus.
FD[13]
is the bidirectional FIFO data bus.
FD[14]
is the bidirectional FIFO data bus.
FD[15]
is the bidirectional FIFO data bus.
34
35
41
42
INT#
SLOE
Output
Input
H
I
36
43
FIFOADR2
Input
I
37
44
FIFOADR0
Input
I
38
45
FIFOADR1
Input
I
39
46
PKTEND
Input
I
40
47
FLAGD/C
S#
FD[0]
FD[1]
FD[2]
FD[3]
FD[4]
FD[5]
FD[6]
FD[7]
FD[8]
FD[9]
FD[10]
FD[11]
FD[12]
FD[13]
FD[14]
FD[15]
CS#:I
FLAGD:O
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
18
19
20
21
22
23
24
25
45
46
47
48
49
50
51
52
25
26
27
28
29
30
31
32
52
53
54
55
56
1
2
3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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