參數(shù)資料
型號(hào)： CY7C68001
廠商： Cypress Semiconductor Corp.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller
中文描述： EZ - USB FX2的USB微控制器的高速USB外設(shè)控制器
文件頁(yè)數(shù)： 15/42頁(yè)
文件大?。?/td> 1588K
代理商： CY7C68001
CY7C68001
Document #: 38-08013 Rev. *H
Page 15 of 42
7.1
IFCONFIG Register 0x01
7.1.1
This bit selects the clock source for the FIFOs. If IFCLKSRC =
0, the external clock on the IFCLK pin is selected. If
IFCLKSRC = 1 (default), an internal 30 or 48 MHz clock is
used.
Bit 7: IFCLKSRC
7.1.2
This bit selects the internal FIFO clock frequency. If 3048MHZ
= 0, the internal clock frequency is 30 MHz. If 3048MHZ = 1
(default), the internal clock frequency is 48 MHz.
Bit 6: 3048MHZ
7.1.3
This bit selects if the IFCLK pin is driven. If IFCLKOE = 0
(default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK
pin is driven.
Bit 5: IFCLKOE
7.1.4
This bit controls the polarity of the IFCLK signal.
When IFCLKPOL=0, the clock has the polarity shown in all
the timing diagrams in this data sheet (rising edge is the
activating edge).
When IFCLKPOL=1, the clock is inverted (in some cases
may help with satisfying data set-up times).
Bit 4: IFCLKPOL
7.1.5
This bit controls whether the FIFO interface is synchronous or
asynchronous. When ASYNC = 0, the FIFOs operate synchro-
nously. In synchronous mode, a clock is supplied either inter-
nally or externally on the IFCLK pin, and the FIFO control
signals function as read and write enable signals for the clock
signal.
Bit 3: ASYNC
When ASYNC = 1 (default), the FIFOs operate asynchro-
nously. No clock signal input to IFCLK is required, and the
FIFO control signals function directly as read and write
strobes.
7.1.6
This bit instructs the
SX2
to enter a low-power mode. When
STANDBY=1, the
SX2
will enter a low-power mode by turning
off its oscillator. The external master should write this bit after
it receives a bus activity interrupt (indicating that the host has
signaled a USB suspend condition). If
SX2
is disconnected
from the USB bus, the external master can write this bit at any
time to save power. Once suspended, the
SX2
is awakened
either by resumption of USB bus activity or by assertion of its
WAKEUP pin.
Bit 2: STANDBY
7.1.7
This bit controls the function of the FLAGD/CS# pin. When
FLAGD/CS# = 0 (default), the pin operates as a slave chip
select. If FLAGD/CS# = 1, the pin operates as FLAGD.
Bit 1: FLAGD/CS#
7.1.8
This bit controls whether the internal pull-up resistor
connected to D+ is pulled high or floating. When DISCON = 1
(default), the pull-up resistor is floating simulating a USB
unplug. When DISCON=0, the pull-up resistor is pulled high
signaling a USB connection.
Bit 0: DISCON
7.2
The
SX2
has four FIFO flags output pins: FLAGA, FLAGB,
FLAGC, FLAGD.
FLAGSAB/FLAGSCD Registers 0x02/0x03
IFCONFIG
0x01
Bit #
7
6
5
4
3
2
1
0
Bit Name
IFCLKSRC
3048MHZ
IFCLKOE
IFCLKPOL
ASYNC
STANDBY
FLAGD/CS#
DISCON
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
0
0
1
0
0
1
FLAGSAB
0x02
Bit #
7
6
5
4
3
2
1
0
Bit Name
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
FLAGSCD
0x03
Bit #
7
6
5
4
3
2
1
0
Bit Name
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
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