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參數(shù)資料
| 型號(hào)： | CY7C68001 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller |
| 中文描述： | EZ - USB FX2的USB微控制器的高速USB外設(shè)控制器 |
| 文件頁(yè)數(shù)： | 18/42頁(yè) |
| 文件大?。?/td> | 1588K |
| 代理商： | CY7C68001 |
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CY7C68001
Document #: 38-08013 Rev. *H
Page 18 of 42
In addition, the EPxPKTLENH register has four other endpoint
configuration bits.
7.6.1
When the external master sets INFM = 1 in an endpoint config-
uration register, the FIFO flags for that endpoint become valid
one sample earlier than when the full condition occurs. These
bits take effect only when the FIFOs are operating synchro-
nously according to an internally or externally supplied clock.
Having the FIFO flag indications one sample early simplifies
some synchronous interfaces. This applies only to IN
endpoints. Default is INFM1 = 0.
Bit 7: INFM1 EPxPKTLENH.7
7.6.2
When the external master sets an OEP = 1 in an endpoint
configuration register, the FIFO flags for that endpoint become
valid one sample earlier than when the empty condition
occurs. These bits take effect only when the FIFOs are
operating synchronously according to an internally or exter-
nally supplied clock. Having the FIFO flag indications one
sample early simplifies some synchronous interfaces. This
applies only to OUT endpoints. Default is OEP1 = 0.
Bit 6: OEP1 EPxPKTLENH.6
7.6.3
When ZEROLEN = 1 (default), a zero length packet will be
sent when the PKTEND pin is asserted and there are no bytes
in the current packet. If ZEROLEN = 0, then a zero length
packet will not be sent under these conditions.
Bit 5: ZEROLEN EPxPKTLENH.5
7.6.4
This bit controls whether the data interface is 8 or 16 bits wide.
If WORDWIDE = 0, the data interface is eight bits wide, and
FD[15:8] have no function. If WORDWIDE = 1 (default), the
data interface is 16 bits wide.
Bit 4: WORDWIDE EPxPKTLENH.4
7.6.5
The default packet size is 512 bytes for all endpoints.
Bit [2..0]: PL[X:0] Packet Length Bits
7.7
The Programmable Flag registers control when the PF goes
active for each of the four endpoint FIFOs: EP2, EP4, EP6,
and EP8. The EPxPFH/L fields are interpreted differently for
the high speed operation and full speed operation and for OUT
and IN endpoints.
Following is the register bit definition for high speed operation
and for full speed operation (when endpoint is configured as
an isochronous endpoint).
EPxPFH/L Registers 0x12–0x19
Following is the bit definition for the same register when the
device is operating at full speed and the endpoint is not
configured as isochronous endpoint.
EPxPKTLENL
0x0B, 0x0D,
0x0F, 0x11
Bit #
7
6
5
4
3
2
1
0
Bit Name
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
EP2PKTLENH,
EP6PKTLENH
0x0A, 0x0E
Bit #
7
6
5
4
3
2
1
0
Bit Name
INFM1 OEP1 ZERO
LEN
WORD
WIDE
0
PL10
PL9
PL8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
1
0
0
1
0
EP4PKTLENH,
EP8PKTLENH
0x0C, 0x10
Bit #
7
6
5
4
3
2
1
0
Bit Name
INFM1 OEP1 ZERO
LEN
WORD
WIDE
0
0
PL9
PL8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
1
0
0
1
0
Full Speed ISO and High Speed Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
7
6
0x13, 0x15,
0x17, 0x19
Bit #
5
4
3
2
1
0
Bit Name
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Full Speed ISO and High Speed Mode:
EP4PFH, EP8PFH
7
0x14, 0x18
Bit #
6
5
4
3
2
1
0
Bit Name
DECIS PKTSTAT
0
IN:
PKTS[1]
OUT:
PFC10
IN:
PKTS[0]
OUT:
PFC9
0
0
PFC8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W R/W R/W
Default
0
0
0
0
1
0
0
0
Full Speed ISO and High Speed Mode:
EP2PFH, EP6PFH
7
0x12, 0x16
Bit #
6
5
4
3
2
1
0
Bit Name
DECIS PKTSTAT
IN:
PKTS[2]
OUT:
PFC12
IN:
PKTS[1]
OUT:
PFC11
IN:
PKTS[0]
OUT:
PFC10
0
PFC9 PFC8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W R/W R/W
Default
1
0
0
0
1
0
0
0
Full Speed Non-ISO Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
7
0x13, 0x15,
0x17, 0x19
Bit #
6
5
4
3
2
1
0
Bit Name
IN:
PKTS[1]
OUT:
PFC7
IN:
PKTS[0]
OUT:
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Full Speed Non-ISO Mode:
EP2PFH, EP6PFH
0x12, 0x16
Bit #
7
6
5
4
3
2
1
0
Bit Name
DECIS PKTSTAT OUT:
PFC12
OUT:
PFC11
OUT:
PFC10
0
PFC9
IN:
PKTS[2]
OUT:
PFC8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
0
0
0
1
0
0
0
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