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參數(shù)資料
| 型號： | CY7C68001 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller |
| 中文描述： | EZ - USB FX2的USB微控制器的高速USB外設控制器 |
| 文件頁數(shù)： | 3/42頁 |
| 文件大小： | 1588K |
| 代理商： | CY7C68001 |
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CY7C68001
Document #: 38-08013 Rev. *H
Page 3 of 42
0xC4
: This initial byte tells the
SX2
that this is a valid EE-
PROM with configuration information.
IFCONFIG
: The IFCONFIG byte contains the settings for
the IFCONFIG register. The IFCONFIG register bits are de-
fined in Section 7.1. If the external master requires an in-
terface configuration different from the default, that interface
can be specified by this byte.
POLAR
: The Polar byte contains the polarity of the FIFO
flag pin signals. The POLAR register bits are defined in
Section 7.3. If the external master requires signal polarity
different from the default, the polarity can be specified by
this byte.
Descriptor
: The Descriptor byte determines if the
SX2
loads the descriptor from the EEPROM. If this byte = 0xC4,
the
SX2
will load the descriptor starting with the next byte.
If this byte does not equal 0xC4, the
SX2
will wait for de-
scriptor information from the external master.
Descriptor Length
: The Descriptor length is within the next
two bytes and indicate the length of the descriptor contained
within the EEPROM. The length is loaded least significant
byte (LSB) first, then most significant byte (MSB).
Byte Index 6 Starts Descriptor Information
: The descrip-
tor can be a maximum of 500 bytes.
3.3.2
An optional default descriptor can be used to simplify enumer-
ation. Only the Vendor ID (VID), Product ID (PID), and Device
ID (DID) need to be loaded by the
SX2
for it to enumerate with
this default set-up. This information is either loaded from an
EEPROM in the case when the presence of an EEPROM
(
Table 3-1
) is detected, or the external master may simply load
a VID, PID, and DID when no EEPROM is present. In this
default enumeration, the
SX2
uses the in-built default
descriptor (refer to Section 12.0).
If the descriptor length loaded from the EEPROM is 6,
SX2
will
load a VID, PID, and DID from the EEPROM and enumerate.
The VID, PID, and DID are loaded LSB, then MSB. For
example, if the VID, PID, and DID are 0x0547, 0x1002, and
0x0001, respectively, then the bytes should be stored as:
0x47, 0x05, 0x02, 0x10, 0x01, 0x00.
If there is no EEPROM,
SX2
will wait for the external master
to provide the descriptor information. To use the default
descriptor, the external master must write to the appropriate
register (0x30) with descriptor length equal to 6 followed by the
VID, PID, and DID. Refer to Section 4.2 for further information
on how the external master may load the values.
The default descriptor enumerates four endpoints as listed in
the following page:
Endpoint 2: Bulk out, 512 bytes in high-speed mode, 64
bytes in full-speed mode
Endpoint 4: Bulk out, 512 bytes in high-speed mode, 64
bytes in full-speed mode
Endpoint 6: Bulk in, 512 bytes in high-speed mode, 64 bytes
in full-speed mode
Endpoint 8: Bulk in, 512 bytes in high-speed mode, 64 bytes
in full-speed mode.
The entire default descriptor is listed in Section 12.0 of this
data sheet.
Default Enumeration
3.4
Interrupt System
3.4.1
The
SX2
provides an output signal that indicates to the
external master that the
SX2
has an interrupt condition, or that
the data from a register read request is available. The
SX2
has
six interrupt sources: SETUP, EP0BUF, FLAGS, ENUMOK,
BUSACTIVITY, and READY. Each interrupt can be enabled or
disabled by setting or clearing the corresponding bit in the
INTENABLE register.
When an interrupt occurs, the INT# pin will be asserted, and
the corresponding bit will be set in the Interrupt Status Byte.
The external master reads the Interrupt Status Byte by
strobing SLRD/SLOE. This presents the Interrupt Status Byte
on the lower portion of the data bus (FD[7:0]). Reading the
Interrupt Status Byte automatically clears the interrupt. Only
one interrupt request will occur at a time; the
SX2
buffers
multiple pending interrupts.
If the external master has initiated a register read request, the
SX2
will buffer interrupts until the external master has read the
data. This insures that after a read sequence has begun, the
next interrupt that is received from the
SX2
will indicate that
the corresponding data is available. Following is a description
of this INTENABLE register.
Architecture
3.4.2
Bit 7: SETUP
If this interrupt is enabled, and the
SX2
receives a set-up
packet from the USB host, the
SX2
asserts the INT# pin and
sets bit 7 in the Interrupt Status Byte. This interrupt only occurs
if the set-up request is not one that the
SX2
automatically
handles. For complete details on how to handle the SETUP
interrupt, refer to Section 5.0 of this data sheet.
Bit 6: EP0BUF
If this interrupt is enabled, and the Endpoint 0 buffer becomes
available to the external master for read or write operations,
the
SX2
asserts the INT# pin and sets bit 6 in the Interrupt
Status Byte. This interrupt is used for handling the data phase
of a set-up request. For complete details on how to handle the
EP0BUF interrupt, refer to Section 5.0 of this data sheet.
Bit 5: FLAGS
If this interrupt is enabled, and any OUT endpoint FIFO’s state
changes from empty to not-empty and from not-empty to
empty, the
SX2
asserts the INT# pin and sets bit 5 in the
Interrupt Status Byte. This is an alternate way to monitor the
status of OUT endpoint FIFOs instead of using the FLAGA-
FLAGD pins, and can be used to indicate when an OUT packet
has been received from the host.
Bit 2: ENUMOK
If this interrupt is enabled and the
SX2
receives a
SET_CONFIGURATION request from the USB host, the
SX2
asserts the INT# pin and sets bit 2 in the Interrupt Status Byte.
This event signals the completion of the
SX2
enumeration
process.
Bit 1: BUSACTIVITY
If this interrupt is enabled, and the
SX2
detects either an
absence or resumption of activity on the USB bus, the
SX2
asserts the INT# pin and sets bit 1 in the Interrupt Status Byte.
This usually indicates that the USB host is either suspending
INTENABLE Register Bit Definition
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