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參數(shù)資料
| 型號(hào)： | CY7C68001 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller |
| 中文描述： | EZ - USB FX2的USB微控制器的高速USB外設(shè)控制器 |
| 文件頁數(shù)： | 2/42頁 |
| 文件大?。?/td> | 1588K |
| 代理商： | CY7C68001 |
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CY7C68001
Document #: 38-08013 Rev. *H
Page 2 of 42
2.2
The EZ-USB
SX2
USB interface device is designed to work
with any external master, such as standard microprocessors,
DSPs, ASICs, and FPGAs to enable USB 2.0 support for any
peripheral design. SX2 has a built-in USB transceiver and
Serial Interface Engine (SIE), along with a command decoder
for sending and receiving USB data. The controller has four
endpoints that share a 4-KB FIFO space for maximum flexi-
bility and throughput, as well as Control Endpoint 0. SX2 has
three address pins and a selectable 8- or 16- bit data bus for
command and data input or output.
Introduction
2.3
System Diagram
3.0
Functional Overview
3.1
SX2
operates at two of the three rates defined in the
Universal
Serial Bus Specification Revision 2.0
, dated April 27, 2000:
Full-speed, with a signaling bit rate of 12 Mbits/s
High-speed, with a signaling bit rate of 480 Mbits/s.
SX2
does not support the low-speed signaling rate of 1.5
Mbits/s.
USB Signaling Speed
3.2
SX2
features:
A selectable 8- or 16-bit bidirectional data bus
An address bus for selecting the FIFO or Command Inter-
face.
Buses
3.3
During the power-up sequence, internal logic of the
SX2
checks for the presence of an I
2
C EEPROM.
[1,2]
If it finds an
EEPROM, it will boot off the EEPROM. When the presence of
an EEPROM is detected, the
SX2
checks the value of first
byte. If the first byte is found to be a 0xC4, the
SX2
loads the
next two bytes into the IFCONFIG and POLAR registers,
respectively. If the fourth byte is also 0xC4, the
SX2
enumerates using the descriptor in the EEPROM, then signals
to the external master when enumeration is complete via an
ENUMOK interrupt (Section 3.4). If no EEPROM is detected,
the
SX2
relies on the external master for the descriptors. Once
this descriptor information is received from the external
master, the
SX2
will connect to the USB and enumerate.
Boot Methods
3.3.1
The valid sequence of bytes in the EEPROM are displayed
below
EEPROM Organization
Notes:
1.
Because there is no direct way to detect which EEPROM type (single or double address) is connected,
SX2
uses the EEPROM address pins A2, A1, and A0
to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and double-
byte EEPROMs (24LC64, etc.) should be strapped to address 001.
The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull-up values are 2.2K–10K
Ohms.
2.
Windows/USB Capable Host
USB Connection
Cypress
SX2
Device CPU
Application
RAM/ROM
EEPROM
USB
Cable
Figure 2-2. Example USB System Diagram
Table 3-1. Descriptor Length Set to 0x06:
Default Enumeration
Byte Index
0
0xC4
1
IFCONFIG
2
POLAR
3
0xC4
4
Descriptor Length (LSB):0x06
5
Descriptor Length (MSB): 0x00
6
VID (LSB)
7
VID (MSB)
8
PID (LSB)
9
PID (MSB)
10
DID (LSB)
11
DID (MSB)
Description
Table 3-2. Descriptor Length Not Set to 0x06
Byte Index
0
0xC4
1
IFCONFIG
2
POLAR
3
0xC4
4
Descriptor Length (LSB)
5
Descriptor Length (MSB
6
Descriptor[0]
7
Descriptor[1]
8
Descriptor[2]
Description
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