參數(shù)資料
型號(hào): CY7C68001
廠商: Cypress Semiconductor Corp.
元件分類(lèi): 基準(zhǔn)電壓源/電流源
英文描述: EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller
中文描述: EZ - USB FX2的USB微控制器的高速USB外設(shè)控制器
文件頁(yè)數(shù): 13/42頁(yè)
文件大?。?/td> 1588K
代理商: CY7C68001
CY7C68001
Document #: 38-08013 Rev. *H
Page 13 of 42
1
8
SLRD
Input
N/A
SLRD
is the input-only read strobe with programmable polarity (POLAR.3) for the
slave FIFOs connected to FD[7:0] or FD[15:0].
SLWR
is the input-only write strobe with programmable polarity (POLAR.2) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
FLAGA
is a programmable slave-FIFO output status flag signal.
Defaults to PF for the FIFO selected by the FIFOADR[2:0] pins.
FLAGB
is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins.
FLAGC
is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins.
Interface Clock
, used for synchronously clocking data into or out of the slave
FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals.
When using the internal clock reference (IFCONFIG.7=1) the IFCLK pin can be
configured to output 30/48 MHz by setting bits IFCONFIG.5 and IFCONFIG.6.
IFCLK may be inverted by setting the bit IFCONFIG.4=1. Programmable polarity.
Reserved
. Must be connected to ground.
USB Wakeup
. If the
SX2
is in suspend, asserting this pin starts up the oscillator
and interrupts the
SX2
to allow it to exit the suspend mode. During normal
operation, holding WAKEUP asserted inhibits the
SX2
chip from suspending. This
pin has programmable polarity (POLAR.7).
I
2
C Clock
. Connect to V
CC
with a 2.2K-10 KOhms resistor, even if no I
2
C
EEPROM is attached.
I
2
C Data
. Connect to V
CC
with a 2.2K-10 KOhms resistor,
even if no I
2
C EEPROM
is attached.
2
9
SLWR
Input
N/A
29
36
FLAGA
Output
H
30
37
FLAGB
Output
H
31
38
FLAGC
Output
H
13
20
IFCLK
I/O/Z
Z
14
44
21
51
Reserved
WAKEUP
Input
Input
N/A
N/A
15
22
SCL
OD
Z
16
23
SDA
OD
Z
55
7
11
17
27
32
43
53
56
10
12
26
28
41
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
Connect to ground
.
Connect to ground
.
Connect to ground
.
Connect to ground
.
Connect to ground
.
Connect to ground
.
Connect to ground
.
14
18
24
34
39
50
4
7
17
19
33
35
48
Table 6-1.
SX2
Pin Definitions
(continued)
QFN
Pin
Pin
Name
SSOP
Type
Default
Description
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