參數(shù)資料
型號(hào)： CY7C68001
廠商： Cypress Semiconductor Corp.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller
中文描述： EZ - USB FX2的USB微控制器的高速USB外設(shè)控制器
文件頁(yè)數(shù)： 33/42頁(yè)
文件大小： 1588K
代理商： CY7C68001
CY7C68001
Document #: 38-08013 Rev. *H
Page 33 of 42
11.6.3
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 11-19
diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the
minimum active pulse of t
RDpwl
and minimum de-active
pulse width of t
RDpwh
. If SLCS is used then, SLCS must be
asserted with SLRD or before SLRD is asserted (i.e., the
SLCS and SLRD signals must both be asserted to start a
valid read condition).
The data that will be driven, after asserting SLRD, is the
updated data from the FIFO. This data is valid after a propa-
gation delay of t
XFD
from the activating edge of SLRD. In
Figure 11-19
, data N is the first valid data read from the
FIFO. For data to appear on the data bus during the read
cycle (i.e. SLRD is asserted), SLOE MUST be in an asserted
state. SLRD and SLOE can also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note
: In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
SLRD
FLAGS
SLOE
DATA
Figure 11-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
t
RDpwh
t
RDpwl
t
OEon
t
XFD
t
XFLG
N
Data (X)
Driven
t
XFD
N+1
t
XFD
t
OEoff
N+3
N+2
t
OEoff
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
t
XFD
t
OEon
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
FAH
t
SFA
N
t=0
T=0
T=1
T=7
T=2
T=3
T=4
T=5
T=6
t=1
t=2
t=3
t=4
N
N
SLOE
SLRD
FIFO POINTER
N+3
FIFO DATA BUS
Not Driven
Driven: X
N
Not Driven
SLOE
N
N+2
N+3
Figure 11-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLRD
N
N+1
SLRD
N+1
SLRD
N+1
N+2
SLRD
N+2
SLRD
N+2
N+1
SLOE
Not Driven
SLOE
N
N+1
N+1
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