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參數(shù)資料
| 型號： | CY7C68001 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller |
| 中文描述： | EZ - USB FX2的USB微控制器的高速USB外設(shè)控制器 |
| 文件頁數(shù)： | 17/42頁 |
| 文件大?。?/td> | 1588K |
| 代理商： | CY7C68001 |
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CY7C68001
Document #: 38-08013 Rev. *H
Page 17 of 42
b. Command data write of upper nibble of the High Byte of
Register Address (0x0E)
c. Command data write of lower nibble of the High Byte of
Register Address (0x06)
3. Send the actual value to write to the register Register (in
this case 0x1C)
a. Command address write of address 0x3C
b. Command data write of upper nibble of the register value
(0x01)
c. Command data write of lower nibble of the register value
(0x0C)
In order to avoid altering any other bits of the FIFOPINPOLAR
register (0xE609) inadvertently, the external master must do a
read (from POLAR register), modify the value to set/clear
appropriate bits and write the modified value to FIFOPIN-
POLAR register. The external master may read from the
POLAR register using the command read protocol as stated in
Section 3.7.8. Modify the value with the appropriate bit set to
change the polarity as needed and write this modified value to
the FIFOPINPOLAR register.
7.4
These register bits define the silicon revision.
REVID Register 0x05
The upper nibble is the major revision. The lower nibble is the
minor revision. For example: if REVID = 0x11, then the silicon
revision is 1.1.
7.5
These registers configure the large, data-handling
SX2
endpoints, EP2, 4, 6, and 8.
Figure 3-1
shows the configu-
ration choices for these endpoints. Shaded blocks group
endpoint buffers for double-, triple-, or quad-buffering. The
endpoint direction is set independently—any shaded block
can have any direction.
EPxCFG Register 0x06–0x09
.
7.5.1
The external master sets VALID = 1 to activate an endpoint,
and VALID = 0 to deactivate it. All
SX2
endpoints default to
valid. An endpoint whose VALID bit is 0 does not respond to
any USB traffic. (Note: when setting VALID=0, use default
values for all other bits.)
Bit 7: VALID
7.5.2
0 = OUT, 1 = IN. Defaults for EP2/4 are DIR = 0, OUT, and for
EP6/8 are DIR = 1, IN.
Bit 6: DIR
7.5.3
These bits define the endpoint type, as shown in
Table 7-3
.
The TYPE bits apply to all of the endpoint configuration
registers. All
SX2
endpoints except EP0 default to BULK.
Bit [5,4]: TYPE1, TYPE0
7.5.4
0 = 512 bytes (default), 1 = 1024 bytes.
Endpoints 4 and 8 can only be 512 bytes and is a read only bit.
The size of endpoints 2 and 6 is selectable.
Bit 3: SIZE
7.5.5
Each bulk endpoint (IN or OUT) has a STALL bit (bit 2). If the
external master sets this bit, any requests to the endpoint
return a STALL handshake rather than ACK or NAK. The Get
Status-Endpoint Request returns the STALL state for the
endpoint indicated in byte 4 of the request. Note that bit 7 of
the endpoint number EP (byte 4) specifies direction.
Bit 2: STALL
7.5.6
For EP2 and EP6 the depth of endpoint buffering is selected
via BUF1:0, as shown in
Table 7-4
. For EP4 and EP8 the
buffer is internally set to double buffered and are read only bits.
Bit [1,0]: BUF1, BUF0
7.6
The external master can use these registers to set smaller
packet sizes than the physical buffer size (refer to the previ-
ously described EPxCFG registers). The default packet size is
512 bytes for all endpoints. Note that EP2 and EP6 can have
maximum sizes of 1024 bytes, and EP4 and EP8 can have
maximum sizes of 512 bytes, to be consistent with the
endpoint structure.
EPxPKTLENH/L Registers 0x0A–0x11
REVID
0x05
Bit #
7
6
5
4
3
2
1
0
Bit
Name
Major
Major
Major
Major
Minor
Minor
Minor
Minor
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
EPxCFG
0x06, 0x08
Bit #
7
6
5
4
3
2
1
0
Bit
Name
VALID
DIR
TYPE1 TYPE0
SIZE
STALL BUF1
BUF0
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
0
1
0
0
0
1
0
EPxCFG
0x07, 0x09
Bit #
7
6
5
4
3
2
1
0
Bit
Name
VALID
DIR
TYPE1 TYPE0
SIZE
STALL BUF1
BUF0
Read/W
rite
R/W
R/W
R/W
R/W
R
R/W
R
R
Default
1
0
1
0
0
0
1
0
Table 7-3. Endpoint Type
TYPE1
0
0
1
1
TYPE0
0
1
0
1
Endpoint Type
Invalid
Isochronous
Bulk (Default)
Interrupt
Table 7-4. Endpoint Buffering
BUF1
0
0
1
1
BUF0
0
1
0
1
Buffering
Quad
Invalid
[10]
Double
Triple
Note:
10. Setting the endpoint buffering to invalid causes improper buffer allocation
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