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參數(shù)資料
| 型號(hào)： | CXD3220R |
| 廠商： | Sony Corporation |
| 英文描述： | IEEE1394 Link/Transaction Layer Controller LSI for SBP-2 |
| 中文描述： | IEEE1394連接鏈路/事務(wù)層控制器芯片為收縮壓- 2 |
| 文件頁數(shù)： | 62/65頁 |
| 文件大?。?/td> | 655K |
| 代理商： | CXD3220R |
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CXD3220R
Bit
Name
0
1
2
3
4 to 7
8 to 15
Arbitration
Reset Gap
Subaction Gap
Bus Reset
State Time-out
Address
Data
Description
Indicates detection of bus idle state for Arbitration Reset Gap Time.
This bit is used by the CXD3220R busy/retry state machine.
Indicates detection of bus idle state for Subaction Gap Time.
This bit is used by the CXD3220R to detect the end of the Isochronous
cycle.
Indicates Phy in bus reset state.
Indicates that Phy state machine is stopped in a certain state for a long time.
Normally used for cable topology loop detection.
Holds the address of the register being read when Phy is trying to send
register contents to the CXD3220R; for example, when responding to Read
via the LReq pin.
Holds the register being sent to the CXD3220R.
Status Bit (Length of Stream: 16bit)
8-2-4. Transmit
When the CXD3220R requests bus access via the LReq pin, Phy performs Arbitration for bus access.
If Phy wins the Arbitration, Transmit is asserted to the Ctl pin for one SYSCLK cycle, and then Idle is asserted
to the Ctl pin for one cycle to give the bus to the CXD3220R. After detecting transmitted state from Phy, the
CXD3220R asserts either Hold or Transmit to the CTL pins to take over interface control. The CXD3220R
asserts Hold until the data is ready, in order to keep bus initiative. During this time, Phy asserts Data-on state
to the bus. When the packet is ready to transmit, the CXD3220R transmits the first bit of the packet, and at the
same time asserts Transmit to the CTL pins. After sending the last bit of the packet, the CXD3220R asserts
either Idle or Hold to the CTL pins for one cycle. Then it asserts Idle for one cycle before these pins become
high impedance.
Here, when it is necessary for the CXD3220R to send another packet without releasing the bus, Hold is
indicated to Phy. In response to this Hold, Phy asserts Transmit in the same way as before after waiting for the
minimum required time.
This function is used after Acknowledge has been sent when the CXD3220R has attempted to send a unified
response or when sending continuous Isochronous packets for one cycle. When sending a multiple number of
packets during a single bus initiative, all packets must be transmitted at the same speed. Consequently,
packet transmission speed is set prior to the first packet.
As described above, when the CXD3220R completes sending the last packet on the newest bus initiative, it
releases the bus by asserting Idle to the CTL pins for 2 SYSCLK. When Phy detects Idle from the CXD3220R,
it starts to assert Idle to CTL for one clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD3300R | 10-bit 20MSPS Video A/D Converter |
| CXD3406GA | Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 2%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| CXD3408 | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| CXD3408GA | Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 5%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD3300R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:10-bit 20MSPS Video A/D Converter |
| CXD3400 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver |
| CXD3400N | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver |
| CXD3406GA | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| CXD3408 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
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