參數(shù)資料
型號(hào)： CXD3220R
廠商： Sony Corporation
英文描述： IEEE1394 Link/Transaction Layer Controller LSI for SBP-2
中文描述： IEEE1394連接鏈路/事務(wù)層控制器芯片為收縮壓- 2
文件頁(yè)數(shù)： 44/65頁(yè)
文件大?。?/td> 655K
代理商： CXD3220R
– 44 –
CXD3220R
7. ADP (Asynchronous Data Pipe)
The CXD3220R is equipped with a function referred to as ADP for automatically transmitting and receiving the
data of computer peripherals in the form of Asynchronous packets based on the SBP-2 protocol.
A dedicated I/O data bus and several control signal pins are used to perform exchange of data with the
decoder/encoder of various systems (see below).
This function also supports the transport data I/F compatible with both 8-bit and 16-bit data.
Name
Width
SD
XHWR
XHRD
SDRQ
XSAC
16
1
1
1
1
I/O
I/O
Input
Input
Output
Input
Description
Data bus
Data write strobe signal
Data read strobe signal
Data request signal
Acknowledge signal for SDRQ
7-1. Built-in FIFO
The CXD3220R is equipped with a built-in dedicated FIFO for SBP2 data transfer.
There are two types of FIFO: a large-capacity FIFO_A and a small-capacity FIFO_B. The capacity of FIFO_A
is 532 quadlets, and is able to contain two 1 KB Asynchronous packets. The capacity of the FIFO_B is 12
quadlets.
Use the CXD3220R with a maximum Asynchronous packet size of 1024 bytes.
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