參數(shù)資料
型號(hào)： CXD3220R
廠商： Sony Corporation
英文描述： IEEE1394 Link/Transaction Layer Controller LSI for SBP-2
中文描述： IEEE1394連接鏈路/事務(wù)層控制器芯片為收縮壓- 2
文件頁(yè)數(shù)： 16/65頁(yè)
文件大?。?/td> 655K
代理商： CXD3220R
– 16 –
CXD3220R
3) Control Register
These registers perform settings for the CXD3220R basic operations.
The register address is 08h; they are for read/write, and the initial value is C600_2A01h.
Bit
Name
31
30
29 to 27
26
25
21
20
13
12
11
10
9
3
0
idVal
RxSld
BsyCtrl
TxEn
RxEn
RstTx
RstRx
AIDT16
AckCtl
CyMasEn
CySrc
CyTEn
StrSid
LPS
Function
Receives packet from the address set in the Node Address register and
packet at bus number "3FFh" node number "3Fh" when "1". Receives packet
at bus number "3FFh" node number "3Fh" only when "0".
Validates reception of Self ID packet when "1". Non-valid when "0".
(Fixed at "1" in the CXD3220R)
Controls Busy status of input packet
000 = Returns Busy according to normal Busy/retry protocol when necessary.
(Fixed at "000" in the CXD3220R)
Transmitter does not transmit Arbitration and packet when "0".
Receiver does not receive packet when "0".
Sync resets transmitter when "1".
This bit is cleared automatically. (Do not use for normal operation.)
Sync resets receiver when "1".
This bit is cleared automatically. (Do not use for normal operation.)
Selects SD bus width. 8 bits when "0" and 16 bits when "1".
Controls the Ack code that is sent back when a packet is received for which
Tcode = 0, 1 (write request quadlet/block).
0: Ack code = 1 (complete), 1: Ack code = 2 (pending)
The Cycle Master function operates if the CXD3220R becomes Root when "1".
Incrementation of the cycle number and reset of Cycle Offset are performed
with Cycle In when "1". Incrementation is performed with Cycle Offset when
"0". (This is always set to "0" internally for this link.)
Validates Cycle Offset increment when "1".
(This is always set to "1" internally for this link.)
Takes received Self ID packet in at the ARF when "1".
Does not take received Self ID packet in to the ARF when "0".
The LPS pin is high when "1".
The LPS pin is low when "0".
相關(guān)PDF資料
PDF描述
CXD3300R 10-bit 20MSPS Video A/D Converter
CXD3406GA Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 2%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes
CXD3408 Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
CXD3408GA Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 5%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes
CXD3412 Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXD3300R 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:10-bit 20MSPS Video A/D Converter
CXD3400 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver
CXD3400N 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver
CXD3406GA 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
CXD3408 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
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