參數(shù)資料
型號(hào)： CXD3220R
廠商： Sony Corporation
英文描述： IEEE1394 Link/Transaction Layer Controller LSI for SBP-2
中文描述： IEEE1394連接鏈路/事務(wù)層控制器芯片為收縮壓- 2
文件頁(yè)數(shù)： 51/65頁(yè)
文件大?。?/td> 655K
代理商： CXD3220R
– 51 –
CXD3220R
7-5. ADP Setting
According to the SBP-2 protocol, a normal command block ORB (shown below) is fetched in the form of a
Block Read response packet from the initiator as a result of the target sending a Block Read response packet
to the initiator.
The Block Read response packet containing the normal command block ORB is incorporated into the ARF in
the format shown below. (Refer to the draft of the Serial Bus Protocol2 (SBP-2) for a detailed explanation
regarding the SBP-2 protocol.)
The following settings are made in the case of automatic data transfer by the ADP after fetching the ORB. To
begin with, there are the 3 modes indicated below for automatic data transfer by the ADP.
Mode 0) Page_table_present (p) = 0, Page_size = 0
When page_table_present (p) = 0, page_size = 0 are set, the ADP enters a transfer mode in which there are
no restrictions on address boundary. In this case, since the address of the initiator is directly indicated in the
data_descriptor obtained with the normal command block ORB, set the node_ID & offset_hi & offset_lo of the
data_descriptor to the Destination ID & destinationOffsetHigh & destinationOffsetLow of the ADP register. Also
set d, spd, max_payload, p, page_size and data_size. ADP transfer starts when the ADPgo bit of the ADP
control register is set to "1".
The transfer speed of request packets generated with the ADP is selected between either S100 for spd = 0 or
S200 for spd = 1.
There are no restrictions on packet size in this mode. Request packets are generated corresponding to the
data_size represented with max_payload, and data is transmitted and received sequentially. Finally, data
corresponding to the number of bytes remaining is transmitted and received with a request packet.
The following page indicates a summary of packetizing with respect to this mode.
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4 3
2
1
1394Header
ORB
Footer
destinationID
rCode
tLabel
next_ORB
tCode
sourceID
next_ORB
data_descriptor
data_descriptor
dataLength
extendedtCode
data_size
command_block
n
d spd
rq_fmt
(0)
max_payload
p page_size
spd
acksent
priority
rt
Basic Configuration
Block Read or Clock Response Receive Format
相關(guān)PDF資料
PDF描述
CXD3300R 10-bit 20MSPS Video A/D Converter
CXD3406GA Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 2%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes
CXD3408 Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
CXD3408GA Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 5%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes
CXD3412 Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXD3300R 制造商:SONY 制造商全稱:Sony Corporation 功能描述:10-bit 20MSPS Video A/D Converter
CXD3400 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver
CXD3400N 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver
CXD3406GA 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
CXD3408 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*