參數(shù)資料
型號(hào): CXD3220R
廠商: Sony Corporation
英文描述: IEEE1394 Link/Transaction Layer Controller LSI for SBP-2
中文描述: IEEE1394連接鏈路/事務(wù)層控制器芯片為收縮壓- 2
文件頁數(shù): 58/65頁
文件大小: 655K
代理商: CXD3220R
– 58 –
CXD3220R
8. Link-Phy Communication
8-1. Link-Phy Interface Specifications
The CXD3220R and Phy Layer chip communicate using the four signals shown in the block diagram below: D
[0:3], CTL [0:1], LREQ and SCLK.
D [0:3]
1394
Link Layer
CXD3220R
1394
Phy Layer
CTL [0:1]
LREQ
SCLK
The roles of the signals are as follows.
D [0:3]
in/out
Bidirectional data line. D [0:1] and D [0:3] are used for 100Mbps and 200Mbps,
respectively.
Bidirectional control line.
Request signal line from the CXD3220R to Phy chip.
Used for bus access and Phy register Read/Write requests.
System clock (49.12MHz) supplied from Phy to the CXD3220R.
CTL [0:1]
LREQ
in/out
out
SYSCLK
in
The types of communication and their contents are described below.
8-2. Communication
There are four types of communication between Phy Link: request, status, transmit and receive. Except for
request, all commands are initialized by the Phy chip.
8-2-1. Bus controlling
CTL [0:1] controls communication between Phy and the CXD3220R. The communication contents differ
depending on if Phy or the CXD3220R is controlling.
a) Phy controlling
CTL [0:1]
Name
00
01
10
11
Idle
Status
Receive
Transmit
Description of Activity
Bus is idle (Default mode).
Phy is sending status information to the CXD3220R.
Phy is sending a packet to the CXD3220R.
Packet transmit authorized for the CXD3220R.
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