參數(shù)資料
型號(hào): CXD3220R
廠商: Sony Corporation
英文描述: IEEE1394 Link/Transaction Layer Controller LSI for SBP-2
中文描述: IEEE1394連接鏈路/事務(wù)層控制器芯片為收縮壓- 2
文件頁數(shù): 43/65頁
文件大小: 655K
代理商: CXD3220R
– 43 –
CXD3220R
6-5-2-3. Block Receive
The format for Block Receive is shown below.
The first quadlet contains the Destination ID and other packet headers. The second and third quadlets contain
16-bit Source ID and 48-bit Destination Offset for request or the Response code for response. The fourth
quadlet contains Data Length and Extended Transaction code (all "0" except for Lock Transaction). This is
followed by Block data. The last quadlet contains packet receive status.
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5 4
3
2
1
destinationID
tLabel
tCode
sourceID
spd
acksent
priority
rt
destinationOffsetHigh
destinationOffsetLow
block data
dataLength
extendedtCode
6-6. Self-ID Packet Receiving Error Processing
In the Self ID phase after bus reset on the CXD3220R, if the Self ID packet could not be received correctly,
Self ID packet receive is stopped immediately and the Node_sum value becomes "0".
The external CPU thus can judge that the Self ID phase could not be completed correctly.
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5 4
3
2
1
destinationID
tLabel
tCode
sourceID
spd
acksent
priority
rt
block data
dataLength
extendedtCode
rCode
Block Write or Lock Request Receive Format
Block Read or Lock Response Receive Format
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