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參數(shù)資料
| 型號： | CXD3220R |
| 廠商： | Sony Corporation |
| 英文描述： | IEEE1394 Link/Transaction Layer Controller LSI for SBP-2 |
| 中文描述： | IEEE1394連接鏈路/事務(wù)層控制器芯片為收縮壓- 2 |
| 文件頁數(shù)： | 38/65頁 |
| 文件大?。?/td> | 655K |
| 代理商： | CXD3220R |
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CXD3220R
6-5-1-4. Unformatted Transmit (Phy Configuration Packet)
The data format for unformatted transmit during Phy Configuration packet transmit is shown below.
The first quadlet contains packet control information. The remaining quadlets contain data, and get on the bus
and are transmitted regardless of format. There is no CRC attached to the packet data.
Further, there is no CRC attached to the first quadlet.
Logical-inverse is not added at Link Core, so it must be added when transmitting.
Field Name
00
phy_ID
R
T
gap_cnt
Description
Indicates that the transmit packet is a Phy configuration packet.
Sets the force_root bit of the node with this Phy_ID sets to "1".
(Only valid when R is set to "1".)
Sets the force_root bit of the node with this Phy_ID to "1" when "1", and clears other
nodes' force_root bit. The Phy_ID area is ignored when "0".
Sets the value of the Phy_CONFIGURATION.gap_Count of the Phy register to the
value of gap_cnt when "1".
Indicates values of all node new Phy_CONFIGURATION.gap_Count.
These values are received immediately and stored in the register. It becomes valid
after the next bus reset.
Unformatted Transmit (Phy Configuration Packet) Fields
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4 3
2
1
tCode
=1110
priority
1
spd
0000
0000
0000
0000
gap_cnt
T
R
00
phy_ID
logical inverse of 2nd quadlet data
Unformatted Transmit Format 1 (Phy Configuration Packet)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD3300R | 10-bit 20MSPS Video A/D Converter |
| CXD3406GA | Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 2%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| CXD3408 | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| CXD3408GA | Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 5%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| CXD3412 | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD3300R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:10-bit 20MSPS Video A/D Converter |
| CXD3400 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver |
| CXD3400N | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver |
| CXD3406GA | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| CXD3408 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
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