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參數(shù)資料
| 型號： | CXD3220R |
| 廠商： | Sony Corporation |
| 英文描述： | IEEE1394 Link/Transaction Layer Controller LSI for SBP-2 |
| 中文描述： | IEEE1394連接鏈路/事務層控制器芯片為收縮壓- 2 |
| 文件頁數(shù)： | 29/65頁 |
| 文件大?。?/td> | 655K |
| 代理商： | CXD3220R |
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CXD3220R
XRD
DATA
AAAA
AAAA
ADDRESS
AAA
AAA
1Ch
1Dh
1Eh
1Fh
XCS
xxxxx0xxb
This indicates no ArfEmpty flags up.
In the above example, ArfEmpty is low.
Data read is possible because the ArfEmpty bit is low.
(3) First quadlet of the received packet Read
The CFR ATFWrite/ARFRead register is read.
XRD
DATA
AAA
AAA
AAA
AAA
74h
ADDRESS
75h
76h
77h
XCS
00h
00h
C0h
FFh
The data read is "FFC00000h".
At this time, the ArfDc bit is high (from (2) above), so this quadlet is the first quadlet.
(2) Confirming that the received packet was stored correctly in FIFO
The CFR Async Status register (1C to 1Fh) is read to confirm that the 26th bit (ArfEmpty bit) is low.
If this bit is high it means that reception may be in progress (all quadlets have not arrived). In this state, do not
read the ARF read register (74 to 77h). Wait some time and again read the Async Status register to confirm
the ArfEmpty bit.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CXD3300R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:10-bit 20MSPS Video A/D Converter |
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| CXD3400N | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver |
| CXD3406GA | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| CXD3408 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
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