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參數(shù)資料
| 型號： | CXD3220R |
| 廠商： | Sony Corporation |
| 英文描述： | IEEE1394 Link/Transaction Layer Controller LSI for SBP-2 |
| 中文描述： | IEEE1394連接鏈路/事務(wù)層控制器芯片為收縮壓- 2 |
| 文件頁數(shù)： | 15/65頁 |
| 文件大?。?/td> | 655K |
| 代理商： | CXD3220R |
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CXD3220R
6-2. CFR (Configuration Register)
This is a memory space to store the status information, operation mode and packet header information in the
chip. Read/write with the external CPU can be performed via the CPU I/F.
The address map and register contents are shown below.
Register Description
1) Version/Revision Register
These registers have the CXD3220R version/revision written in them.
The register address is 00h; they are read only, and the default value is 3220_0000h.
Bit
Name
31 to 16
15 to 0
Version
Revision
Function
CXD3220R version number
CXD3220R revision number
2) Node Address Register
These registers are used to monitor root/cycle master status and the total number of nodes connected, and so
on.
The register address is 04h and the initial value is FFFF_0000h.
Only the bus number is for read/write, and the other registers are normally for read only, but the Diagnostic
register can be read/write by setting regRW to "1".
Bit
Name
31 to 22
21 to 16
15
14
13
11 to 6
5 to 0
Bus Number
Node Number
root
Power Status
CyMas
NodeSum
CFMcontID
Function
Bus number of connected bus
Node number of this link
Root/not root for this link
1: root; 0: not root
Cable power status for this mode
1: CPS on; 0: CPS off
Whether or not this link is cycle master
1: cycle master; 0: not
Total number of connected nodes. The value becomes "0" when an error
occurs in the Self ID phase. This value is fixed when the Interrupt register
EndSlf bit becomes "1" from "0".
The Phy-ID value of the contender is loaded.
However, when the CXD3220R node has an ability to become the contender
and this LSI has the Phy-ID value larger than the loaded value, the CXD3220R
itself is the contender. This value is fixed when the Interrupt register EndSlf
bit becomes "1" from "0".
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD3300R | 10-bit 20MSPS Video A/D Converter |
| CXD3406GA | Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 2%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
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| CXD3408GA | Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 5%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| CXD3412 | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD3300R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:10-bit 20MSPS Video A/D Converter |
| CXD3400 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver |
| CXD3400N | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:6-channel CCD Vertical Clock Driver |
| CXD3406GA | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| CXD3408 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
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