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參數(shù)資料
| 型號(hào)： | BX80528KL150GD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封裝： | PGA-603 |
| 文件頁(yè)數(shù)： | 97/116頁(yè) |
| 文件大小： | 2277K |
| 代理商： | BX80528KL150GD |
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Intel XeonTM Processor MP
Datasheet
81
BR0#
BR[1:3]#
I/O
I
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]#
signals are interconnected in a rotating manner to individual processor pins. The tables
below give the rotating interconnect between the processor and bus signals for 2-way and 4-
way systems.
During power-on configuration, the central agent must assert the BREQ0# bus signal. All
symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition of
RESET#. The pin which the agent samples asserted determines it’s agent ID.
These signals do not have on-die termination and must be terminated at the end agent.
COMP[1:0]
I
COMP[1:0] must be terminated to VSS on the system board using precision resistors. These
inputs configure the AGTL+ drivers of the processor. Refer to the appropriate platform
design guidelines and Table 12 for implementation details.
D[63:0]#
I/O
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the
processor system bus agents, and must connect the appropriate pins on all such agents. The
data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock
period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#.
Each groupof16datasignals correspondtoapair of oneDSTBP#and one DSTBN#. The
following table shows the grouping of data signals to strobes and DBI#.
Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data
signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding
data group is inverted and therefore sampled active high.
Table 33. Signal Definitions (Page 3 of 8)
Name
Type
Description
BR[3:0]# Signals Rotating Interconnect, 4-way system (Intel Xeon processor MP
processors only)
Bus Signal
Agent 0 Pins
Agent 1 Pins
Agent 2 pins
Agent 3 pins
BREQ0#
BR0#
BR3#
BR2#
BR1#
BREQ1#
BR1#
BR0#
BR3#
BR2#
BREQ2#
BR2#
BR1#
BR0#
BR3#
BREQ3#
BR3#
BR2#
BR1#
BR0#
Data Group
DSTBN/DSTBP
DBI#
D[15:0]#
0
D[31:16]#
1
D[47:32]#
2
D[63:48]#
3
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