- 您現在的位置：買賣IC網 > PDF目錄256256 > BX80528KL150GD (INTEL CORP) 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA603 PDF資料下載
參數資料
| 型號： | BX80528KL150GD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封裝： | PGA-603 |
| 文件頁數： | 100/116頁 |
| 文件大?。?/td> | 2277K |
| 代理商： | BX80528KL150GD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁當前第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁
Intel XeonTM Processor MP
84
Datasheet
PROCHOT#
O
PROCHOT# (processor hot) indicates that the processor Thermal Control Circuit (TCC) has
been activated. Under most conditions, PROCHOT# will go active when the processor’s
thermal sensor detects that the processor has reached its maximum safe operating
temperature. See Section 7.3 for more details.
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean
indication that the clocks and power supplies are stable and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state. Figure 10
illustrates the relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 15,
andbe followedbya 1ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect internal
circuits against voltage sequencing issues. It should be driven high throughout boundary
scan operation.
REQ[4:0]#
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor system
bus agents. They are asserted by the current bus owner to define the currently active
transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the
AP[1:0]# signal description for details on parity checking of these signals.
RESET#
I
Asserting the RESET# signal resets all processors to known states and invalidates their
internal caches without writing back any of their contents. For a power-on Reset, RESET#
must stay active for at least one millisecond after VCC and BCLK have reached their proper
specifications. On observing active RESET#, all system bus agents will deassert their
outputs within two clocks. RESET# must not be kept asserted for more than 10ms.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for
power-on configuration. These configuration options are described in the Section 7.1.
This signal does not have on-die termination and must be terminated at the end agent.
RS[2:0]#
I
RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for
completion of the current transaction), and must connect the appropriate pins of all
processor system bus agents.
RSP#
I
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for which
RSP# provides parity protection. It must connect to the appropriate pins of all processor
system bus agents.
A correct parity signal is high if an even number of covered signals are low and low if an
odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this
indicates it is not being driven by any agent guaranteeing correct parity.
SKTOCC#
O
SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that the
processor is present.
SLP#
I
SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the Sleep state.
During Sleep state, the processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this state will not
recognize snoops or interrupts. The processor will recognize only assertion of the RESET#
signal or deassertion of SLP#. If SLP# is deasserted, the processor exits Sleep state and
returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core
units.
SM_ALERT#
O
SM_ALERT# is an asynchronous interrupt line associated with the SMBus Thermal Sensor
device. It is an open-drain output and the processor includes a 10k
pull-up resistor to
SM_VCC for this signal. For more information on the usage of the SM_ALERT# pin, see
SM_CLK
I/O
The SM_CLK (SMBus Clock) signal is an input clock to the system management logic
which is required for operation of the system management features of the Intel Xeon
processor. This clock is driven by the SMBus controller and is asynchronous to other clocks
in the processor.The processor includes a 10k
pull-up resistor to SM_V
CC for this signal.
Table 33. Signal Definitions (Page 6 of 8)
Name
Type
Description
相關PDF資料 |
PDF描述 |
|---|---|
| BU-61740B3-200L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61740B4-200L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61740B4-400L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61840B3-300 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61840B3-302W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| BX80530C1000256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| BX80530C1133256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| BX80530C1200256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| BX80530C1400512 | 制造商:Intel 功能描述:MPU PENTIUM III PROCESSOR 64-BIT 0.13UM 1.4GHZ 370-PIN FCPG - Boxed Product (Development Kits) |
| BX80530F1100256 | 制造商:Intel 功能描述:CELERON PROCESSOR - Boxed Product (Development Kits) |
發(fā)布緊急采購，3分鐘左右您將得到回復。