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參數(shù)資料
| 型號(hào)： | BX80528KL150GD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封裝： | PGA-603 |
| 文件頁數(shù)： | 1/116頁 |
| 文件大?。?/td> | 2277K |
| 代理商： | BX80528KL150GD |
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Intel Xeon Processor MP
at 1.40 GHz, 1.50 GHz and 1.60 GHz
Datasheet
Product Features
The Intel
Xeon processor MP is designed for high-performance enterprise and e-Business
server applications. Based on the Intel
NetBurst micro-architecture, it is binary compatible
with previous Intel IA-32 Architecture processors and introduces Hyper-Threading technology
to multi-processing server platforms. The Intel Xeon processor MP is scalable to four of more
processors in a multiprocessor system providing exceptional performance for enterprise server
applications running on advanced operating systems such as Windows 2000 Server*, Linux*,
Netware* and UNIX*. The Intel Xeon processor MP extends the power of the Intel
Pentium
III Xeon processor with new features designed to make this processor the right choice for
powerful enterprise server, and mission-critical applications. Advanced features simplify system
management and meet the needs of a robust IT environment, resulting in maximized system up
time, convenient system management, and optimal configuration.
s
Available at 1.40, 1.50 and 1.60GHz
s
4-way and greater multi-processing server
support
s
Binary compatible with applications
running on Intel IA-32 architecture
processors
s
Hyper-Threading Technology enabling
multi-threading server software to execute
threads in parallel on each processor
s
400 MHz system bus
— Bandwidth up to 3.2 Gbytes/sec
s
Rapid Execution Engine: Arithmetic Logic
Units (ALUs) run at twice the processor
core frequency
s
Enables system support of up to 64 GB of
physical memory
s
Advance Dynamic Execution
— Very deep out-of-order execution
— Enhanced branch prediction
s
Level 1 Execution Trace Cache stores 12 K
micro-ops and removes decoder latency
from main execution loops
— Includes 8 KB Level 1 data cache
s
Intel
NetBurst micro-architecture
s
256 KB Advanced Transfer Cache (on-die,
full speed Level 2 (L2) cache) with 8-way
associativity and Error Correcting Code
(ECC)
s
512 KB or 1 MB of Integrated Level 3
Cache (on-die, full speed Level 3 Cache)
with Error Correcting Code (ECC) provides
faster access to large server instruction and
data sets
s
144 new Streaming SIMD Extensions 2
(SSE2) instructions
s
Enhanced floating point and multimedia
unit for enhanced video, audio, encryption,
and 3D performance
s
Power Management capabilities
— System Management mode
— Multiple low-power states
s
Advanced System Management Features
— Processor Information ROM (PIROM)
— System Management Bus (SMBus)
— OEM Scratch EEPROM
— Machine Check Architecture (MCA)
Order Number: 290740-002
March 2002
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