參數(shù)資料
型號： BX80528KL150GD
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA603
封裝： PGA-603
文件頁數(shù)： 32/116頁
文件大小： 2277K
代理商： BX80528KL150GD
Intel XeonTM Processor MP
22
Datasheet
NOTES:
1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signals are not terminated by the processor. Refer to the ITP700 Debug Port Design Guide and the
platform design guidelines for termination recommendations.They must be terminated at the end agents by the platform.
3. These signal groups are not terminated by the processor. Refer to Section 2.6,the ITP700 Debug Port Design Guide,
and the platform design guidelines for termination recommendations.
4. This signal group is not terminated by the processor. Refer to Section 2.6 and the platform design guidelines for
termination recommendations.
5. The value on these pins during the active-to-inactive edge of RESET# determines the multiplier that the Phase Lock
Loop (PLL) will use for the internal core clock.
6. The value of these pins during the active-to-inactive edge of RESET# determine processor configuration options. See
Section 7.1 for details.
7. These signals may be driven simultaneously by multiple agents (wired-OR).
8. These signals are not terminated by the processor’s on-die termination. However, some signals in this group include
termination on the processor interposer. See Section 7.4 for details.
Table 4.
System Bus Signal Groups
Signal Group
Type
Signals
1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#2, DEFER#, RESET#2, RS[2:0]#,
RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#7,BNR#7, BPM[5:0]#2,
BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#7,
HITM#7,LOCK#,MCERR#7
AGTL+ Source Synchronous I/O
Synchronous to assoc. strobe
AGTL+ Strobes
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+ Input
3
Asynchronous
A20M#
5, IGNNE#5,INIT#6,LINT0/INTR5,
LINT1/NMI
5, PWRGOOD, SMI#6,SLP#,
STPCLK#
Asynchronous GTL+ Output
4
Asynchronous
FERR#, IERR#, THERMTRIP#, PROCHOT#
System Bus Clock
Clock
BCLK1, BCLK0
TAP Input
3
Synchronous to TCK
TCK, TDI, TMS, TRST#
TAP Output
3
Synchronous to TCK
TDO
SMBus Interface
8
Synchronous to SM_CLK
SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT,
SM_CLK, SM_ALERT#, SM_WP
Power/Other
COMP[1:0], GTLREF, OTDEN, Reserved,
SKTOCC#, TESTHI[6:0],VID[4:0], V
CC,
SM_VCC, V
CCA,VSSA,VCCIOPLL,VSS,VCCSENSE,
V
SSSENSE
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#
6
ADSTB0#
A[35:17]#
6
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#
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