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9
ATA6020N
4708A–4BMCU–06/03
Table 1.
Interrupt Priority Table
Interrupt
INT0
Software Interrupts
The programmer can generate interrupts by using the software interrupt instruction
(SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. The
software triggered interrupt operates exactly like any hardware triggered interrupt. The
SWI instruction takes the top two elements from the expression stack and writes the cor-
responding bits via the I/O bus to the interrupt pending register. Therefore, by using the
SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for
later execution.
Hardware Interrupts
In the ATA6020N, there are eleven hardware interrupt sources with seven different lev-
els. Each source can be masked individually by mask bits in the corresponding control
registers. An overview of the possible hardware configurations is shown in Table 8.
Priority
lowest
ROM Address
040h
Interrupt Opcode
C8h (SCALL 040h)
Function
Software interrupt (SWI0)
External hardware interrupt, any
edge at BP52 or BP53
Timer 1 interrupt
SSI interrupt or external
hardware interrupt at BP40 or
BP43
Timer 2 interrupt
Software interrupt (SW15)
External hardware interrupt, at
any edge at BP50 or BP51
Voltage monitor (VM) interrupt
INT1
|
080h
D0h (SCALL 080h)
INT2
|
0C0h
D8h (SCALL 0C0h)
INT3
|
100h
E8h (SCALL 100h)
INT4
INT5
|
|
140h
180h
E8h (SCALL 140h)
F0h (SCALL 180h)
INT6
1C0h
F8h (SCALL 1C0h)
INT7
highest
1E0h
FCh (SCALL 1E0h)
Table 2.
Hardware Interrupts
Interrupt
Interrupt Mask
Interrupt Source
Any edge at BP52
Any edge at BP53
Timer 1
SSI buffer full/empty or
BP40/BP43 interrupt
Timer 2 compare match/overflow
Any edge at BP50
Any edge at BP51
External/internal voltage
monitoring
Register
Bit
INT1
P5CR
P52M1, P52M2
P53M1, P53M2
T1IM
SIM
INT2
T1M
INT3
SISC
INT4
T2CM
T2IM
INT6
P5CR
P50M1, P50M2
P51M1, P51M2
VIM
INT7
VCM