參數(shù)資料
型號(hào)： ATA6020N
英文描述： ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog
中文描述： ATA6020N [更新6月3日。 58頁(yè)]可編程的看門(mén)狗
文件頁(yè)數(shù)： 8/58頁(yè)
文件大小： 898K
代理商： ATA6020N
8
ATA6020N
4708A–4BMCU–06/03
Figure 8.
Interrupt Handling
Interrupt Processing
In order to process the eight interrupt levels, the MARC4 includes an interrupt controller
with two 8-bit wide interrupt pending and interrupt active registers. The interrupt control-
ler samples all interrupt requests during every non-I/O instruction cycle and latches
these in the interrupt pending register. If no higher priority interrupt is present in the
interrupt active register, it signals the CPU to interrupt the current program execution. If
the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. Dur-
ing this cycle a short call (SCALL) instruction to the service routine is executed and the
current PC is saved on the return stack. An interrupt service routine is completed with
the RTI instruction. This instruction resets the corresponding bits in the interrupt pend-
ing/active register and fetches the return address from the return stack to the program
counter. When the interrupt enable flag is reset (triggering of interrupt routines are dis-
abled), the execution of new interrupt service routines is inhibited but not the logging of
the interrupt requests in the interrupt pending register. The execution of the interrupt is
delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an
interrupt request occurs while the corresponding bit in the pending register is still set
(i.e., the interrupt service routine is not yet finished).
It should be noted that automatic stacking of the RBR is not carried out by the hardware
and so if ROM banking is used, the RBR must be stacked on the expression stack by
the application program and restored before the RTI. After a master reset (power-on,
brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and
interrupt active register are all reset.
Interrupt Latency
The interrupt latency is the time from the occurrence of the interrupt to the interrupt ser-
vice routine being activated. This is extremely short (taking between 3 to 5 machine
cycles depending on the state of the core).
7
6
5
4
3
2
1
0
P
INT5 active
INT7 active
INT2 pending
SWI0
INT2 active
INT0 pending
INT0 active
INT2
RTI
RTI
INT5
INT3 active
INT3
RTI
RTI
RTI
INT7
Time
Main /
Autosleep
Main /
Autosleep
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