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參數(shù)資料
| 型號： | ATA6020N |
| 英文描述： | ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog |
| 中文描述： | ATA6020N [更新6月3日。 58頁]可編程的看門狗 |
| 文件頁數(shù)： | 14/58頁 |
| 文件大?。?/td> | 898K |
| 代理商： | ATA6020N |
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14
ATA6020N
4708A–4BMCU–06/03
Figure 14.
Clock Module
Table 4.
Clock Modes
The clock module generates two output clocks. One is the system clock (SYSCL) and
the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals
and the SUBCL can supply only the peripherals with clocks. The modes for clock
sources are programmable with the OS1-bit and OS0-bit in the SC-register and the
CCS-bit in the CM-register.
Oscillator Circuits and
External Clock Input
Stage
The ATA6020N consists of two different internal RC-oscillators and one external clock
input stage.
RC-oscillator 1 Fully
Integrated
For timing insensitive applications, it is possible to use the fully integrated RC-
oscillator 1. It operates without any external components and saves additional costs.
The RC-oscillator 1 center frequency tolerance is better than ±50% over the full temper-
ature and voltage range.
The basic center frequency of the RC-oscillator 1 is f
O
4.0 MHz The RC-oscillator 1 is
selected by default after power-on reset.
Ext. clock
ExIn
Stop
RC oscillator2
Stop
R
Trim
Oscin
RC
oscillator 1
Control
Stop
IN1
IN2
Cin
/2
/2
/2
/2
/2
/2
/2
/2
Divider
WDL
Osc-Stop
NSTOP
CCS
CSS1
CSS0
CM:
BOT
- - -
OS1
OS0
SUBCL
SYSCL
SC:
OSC1
Cin/16
ExOut
RCOut2
RCOut1
Sleep
Mode
OS1
OS0
Clock Source for SYSCL
CCS = 1
RC-oscillator 1
(internal)
RC-oscillator 1
(internal)
Clock Source
for SUBCL
CCS = 0
1
1
1
External input clock
C
in
/16
2
0
1
RC-oscillator 2 with
external trimming resistor
C
in
/16
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