參數(shù)資料
型號: ATA6020N
英文描述: ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog
中文描述: ATA6020N [更新6月3日。 58頁]可編程的看門狗
文件頁數(shù): 3/58頁
文件大?。?/td> 898K
代理商: ATA6020N
3
ATA6020N
4708A–4BMCU–06/03
Introduction
The ATA6020N is a member of Atmel’s 4-bit single-chip microcontroller family. It con-
tains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter,
voltage supervisor, interval timer with watchdog function and a sophisticated on-chip
clock generation with integrated RC-oscillators.
MARC4 Architecture
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and
on-chip peripherals. The CPU is based on the HARVARD architecture with physically
separated program memory (ROM) and data memory (RAM). Three independent
buses, the instruction bus, the memory bus and the I/O bus, are used for parallel com-
munication between ROM, RAM and peripherals. This enhances program execution
speed by allowing both instruction prefetching, and a simultaneous communication to
the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller
with associated eight prioritized interrupt levels supports fast and efficient processing of
hardware events. The MARC4 is designed for the high-level programming language
qFORTH. The core includes both, an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 3.
MARC4 Core
Instruction
decoder
CCR
TOS
ALU
RAM
256 x 4-bit
PC
RP
SP
X
Y
Program
memory
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
Reset
System
clock
Interrupt
controller
On-chip peripheral modules
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