參數(shù)資料
型號: ATA6020N
英文描述: ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog
中文描述: ATA6020N [更新6月3日。 58頁]可編程的看門狗
文件頁數(shù): 30/58頁
文件大?。?/td> 898K
代理商: ATA6020N
30
ATA6020N
4708A–4BMCU–06/03
Figure 26.
Timer 2
Timer 2 Modes
Mode 1: 12-bit Compare
Counter
The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A com-
pare match signal of the 4-bit and the 8-bit stage generates the signal for the counter
reset, toggle flip-flop or interrupt. The compare action is programmable via the compare
mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output
(POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.
Figure 27.
12-bit Compare Counter
4-bit Counter 2/1
RES
OVF1
Compare 2/1
T2CO1
CM1
POUT
SSI POUT
CL2/2
DCG
T2M1
P4CR
8-bit Counter 2/2
RES
OVF2
Compare 2/2
T2CO2
T2CM
Control
TOG2
INT4
Biphase-,
Manchester-
modulator
OUTPUT
MOUT
M2
to
Modulator 3
T2O
Timer 2
modulator
output-stage
T2M2
SO
Control
SSI
SSI
I/O-bus
T2C
CL2/1
T2I
SYSCL
T1OUT
SCL
I/O-bus
DCGO
4-bit counter
4-bit compare
RES
4-bit register
CM1
POUT (CL2/1 /16)
8-bit counter
8-bit compare
8-bit register
OVF2
CM2
RES
T2RM
T2OTM
Timer 2
output mode
and T2OTM-bit
T2IM
T2CTM
TOG2
INT4
CL2/1
DCG
T2D1, 0
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