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參數(shù)資料
| 型號： | ATA6020N |
| 英文描述： | ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog |
| 中文描述： | ATA6020N [更新6月3日。 58頁]可編程的看門狗 |
| 文件頁數(shù)： | 11/58頁 |
| 文件大?。?/td> | 898K |
| 代理商： | ATA6020N |
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11
ATA6020N
4708A–4BMCU–06/03
A power-on reset pulse is generated by a V
DD
rise across the default BOT voltage level
(3.0 V). A brown-out reset pulse is generated when V
DD
falls below the brown-out volt-
age threshold. Two values for the brown-out voltage threshold are programmable via
the BOT-bit in the SC-register. When the controller runs in the upper supply voltage
range with a high system clock frequency, the high threshold must be used. When it
runs with a lower system clock frequency, the low threshold and a wider supply voltage
range may be chosen. For further details, see the electrical specification and the SC-
register description for BOT programming.
Figure 10.
Brown-out Detection
BOT = 1, low brown-out voltage threshold. (3.0 V is the reset value).
BOT = 0, high brown-out voltage threshold (4.0 V).
Watchdog Reset
The watchdog's function can be enabled at the WDC-register and triggers a reset with
every watchdog counter overflow. To suppress the watchdog reset, the watchdog
counter must be regularly reset by reading the watchdog register address (CWD). The
CPU reacts in exactly the same manner as a reset stimulus from any of the above
sources.
External Clock Supervisor
The external input clock supervisor function can be enabled if the external input clock is
selected within the CM- and SC-registers of the clock module. The CPU reacts in
exactly the same manner as a reset stimulus from any of the above sources.
Voltage Monitor
The voltage monitor consists of a comparator with internal voltage reference. It is used
to supervise the supply voltage or an external voltage at the VMI pin. The comparator for
the supply voltage has two internal programmable thresholds: one lower threshold
(4.0 V) and one higher threshold (5.0 V). For external voltages at the VMI pin, the com-
parator threshold is set to V
BG
= 1.25 V. The VMS-bit indicates if the supervised voltage
is below (VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated
when the VMS-bit is set or reset to detect a rising or falling slope. A voltage monitor
interrupt (INT7) is enabled when the interrupt mask bit (VIM) is reset in the VMC-
register.
VDD
CPU
Reset
t
BOT = '1'
4.0 V
3.0 V
CPU
Reset
BOT = '0'
td
td
td = 1.5 ms (typically)
td
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