參數(shù)資料
型號: ATA6020N
英文描述: ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog
中文描述: ATA6020N [更新6月3日。 58頁]可編程的看門狗
文件頁數(shù): 5/58頁
文件大?。?/td> 898K
代理商: ATA6020N
5
ATA6020N
4708A–4BMCU–06/03
Expression Stack
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All
arithmetic, I/O and memory reference operations take their operands, and return their
results to the expression stack. The MARC4 performs the operations with the top of
stack items (TOS and TOS-1). The TOS register contains the top element of the expres-
sion stack and works in the same way as an accumulator. This stack is also used for
passing parameters between subroutines and as a scratch pad area for temporary stor-
age of data.
Return Stack
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for
storing return addresses of subroutines, interrupt routines and for keeping loop index
counts. The return stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of
the expression stack and the return stack. The two stacks within the RAM have a user
definable location and maximum depth.
Registers
The MARC4 controller has seven programmable registers and one condition code regis-
ter. They are shown in the following programming model.
Program Counter (PC)
The program counter is a 12-bit register which contains the address of the next instruc-
tion to be fetched from ROM. Instructions currently being executed are decoded in the
instruction decoder to determine the internal micro-operations. For linear code (no calls
or branches) the program counter is incremented with every instruction cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address. The program counter is also used with the TABLE instruc-
tion to fetch 8-bit wide ROM constants.
Figure 6.
Programming Model
RAM Address Registers
The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y.
These registers allow access to any of the 256 RAM nibbles.
TOS
CCR
0
3
0
3
0
7
0
7
7
0
11
RP
SP
X
Y
PC
--
B
I
Program counter
Return stack pointer
Expression stack pointer
RAM address register (X)
RAM address register (Y)
Top of stack register
Condition code register
Interrupt enable
Carry/borrow
Branch
Reserved
0
7
C
0
0
0
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