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參數(shù)資料
| 型號(hào)： | ATA6020N |
| 英文描述： | ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog |
| 中文描述： | ATA6020N [更新6月3日。 58頁]可編程的看門狗 |
| 文件頁數(shù)： | 43/58頁 |
| 文件大小： | 898K |
| 代理商： | ATA6020N |
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43
ATA6020N
4708A–4BMCU–06/03
Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate
data direction for the first word must be set using the SDD control bit. The state of this
bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data
bits are, depending on the selected direction, either clocked into or out of the shift regis-
ter. During the 9th clock period, the port direction is automatically switched over so that
the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the
acknowledge bit received from the device is captured in the SSI Status Register (TACK)
where it can be read by the controller. A receive mode, the state of the acknowledge bit
to be returned to the device is predetermined by the SSI Status Register (RACK ).
Changing the directional mode (TX/RX) should not be performed during the transfer of
an MCL telegram. One should wait until the end of the telegram which can be detected
using the SSI interrupt (IFN = 1) or by interrogating the ACT status.
A 9-bit telegram, once started will always run to completion and will not be prematurely
terminated by the SIR bit. So, if the SIR-bit is set to '1' in with telegram, the SSI will com-
plete the current transfer and terminate the dialog with an MCL stop condition.
Figure 44.
Example of MCL Transmit Dialog
7 6 5 4 3 2 1
7 6 5 4 3 2 1 0 A
msb
lsb
tx data 1
tx data 2
msb
lsb
Write STB
(tx data 1)
SC
SD
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
0 A
Write STB
(tx data 2)
SIR
SDD
Start
Stop
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