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參數(shù)資料
| 型號(hào)： | ATA6020N |
| 英文描述： | ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog |
| 中文描述： | ATA6020N [更新6月3日。 58頁]可編程的看門狗 |
| 文件頁數(shù)： | 37/58頁 |
| 文件大?。?/td> | 898K |
| 代理商： | ATA6020N |
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37
ATA6020N
4708A–4BMCU–06/03
Figure 39.
DCG Output Signals
Timer 2 Mode Register 2
(T2M2)
Table 18.
Output
Mode
Note:
If one of these output modes is used the T2O alternate function of Port 4 must also be
activated.
DCGIN
DCGO0
DCGO1
DCGO2
DCGO3
Address: ’7’hex — Subaddress: ’2’hex
T2M2
Bit 3
T2TOP
Bit 2
T2OS2
Bit 1
T2OS1
Bit 0
T2OS0
Reset value: 1111b
T2TOP
T
imer
2
T
oggle
O
utput
P
reset
This bit allows the programmer to preset the Timer 2 output T2O.
T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)
T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)
Note: If T2R = 1, no output preset is possible
T
imer
2
O
utput
S
elect bit
2
T
imer
2
O
utput
S
elect bit
1
T
imer
2
O
utput
S
elect bit
0
T2OS2
T2OS1
T2OS0
T2OS2
T2MS1
T2MS0
Clock Output (POUT)
Toggle mode: a Timer 2 compare match
toggles the output flip-flop (M2) -> T2O
Duty cycle burst generator 1: the DCG
output signal (DCG0) is given to the output
and gated by the output flip-flop (M2)
Duty cycle burst generator 2: the DCG
output signal (DCGO) is given to the output
and gated by the SSI internal data output
(SO)
Bi-phase modulator: Timer 2 modulates
the SSI internal data output (SO) to
Bi-phase code
Manchester modulator: Timer 2 modulates
the SSI internal data output (SO) to
Manchester code
SSI output: T2O is used directly as SSI
internal data output (SO)
PWM mode: an 8/12-bit PWM mode
Not allowed
1
1
1
1
2
1
1
0
3
1
0
1
4
1
0
0
5
0
1
1
6
0
1
0
7
8
0
0
0
0
1
0
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