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參數(shù)資料
| 型號： | ATA6020N |
| 英文描述： | ATA6020N [Updated 6/03. 58 Pages]Programmable Watchdog |
| 中文描述： | ATA6020N [更新6月3日。 58頁]可編程的看門狗 |
| 文件頁數(shù)： | 38/58頁 |
| 文件大?。?/td> | 898K |
| 代理商： | ATA6020N |
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38
ATA6020N
4708A–4BMCU–06/03
Timer 2 Compare and
Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for
the 8-bit stage of Timer 2. The timer compares the contents of the compare register cur-
rent counter value and if it matches it generates an output signal. Depending on the
timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop
as SSI clock or as a clock for the next counter stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit
compare value. In all other modes, the two compare registers work independently as a
4-bit and 8-bit compare register. When assigned to the compare register a compare
event will be suppressed.
Timer 2 Compare Mode
Register (T2CM)
Table 19.
Timer 2 Output Mode
1, 2, 3, 4, 5 and 6
1, 2, 3, 4, 5 and 6
Timer 2 COmpare Register 1
(T2CO1)
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Address: ’7’hex — Subaddress: ’3’hex
T2CM
Bit 3
T2OTM
Bit 2
T2CTM
Bit 1
T2RM
Bit 0
T2IM
Reset value: 0000b
T2OTM
T
imer
2
O
verflow
T
oggle
M
ask bit
T2OTM = 0, disable overflow toggle
T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles the output
flip-flop (TOG2). If the T2OTM-bit is set, only a counter overflow
can generate an interrupt except on the Timer 2 output mode 7.
T
imer
2
C
ompare
T
oggle
M
ask bit
T2CTM = 0, disable compare toggle
T2CTM = 1, enable compare toggle, a match of the counter with the compare
register toggles output flip-flop (TOG2). In Timer 2 output mode 7
and when the T2CTM-bit is set, only a match of the counter with the
compare register can generate an interrupt.
T
imer
2
R
eset
M
ask bit
T2RM = 0, disable counter reset
T2RM = 1, enable counter reset, a match of the counter with the compare register
resets the counter
T
imer
2
I
nterrupt
M
ask bit
T2IM = 0, disable Timer 2 interrupt
T2IM = 1, enable Timer 2 interrupt
T2CTM
T2RM
T2IM
T2OTM
0
1
x
T2CTM
x
x
1
Timer 2 Interrupt Source
Compare match (CM2)
Overflow (OVF2)
Compare match (CM2)
7
Address: ’7’hex —
Subaddress: ’4’hex
Reset value: 1111b
T2CO1
Write cycle
Bit 3
Bit 2
Bit 1
Bit 0
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