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45
ATA6020N
4708A–4BMCU–06/03
Figure 46.
MCL Bus Protocol 1
Bus not busy (1)
Both data and clock lines remain HIGH.
Start data transfer (2)
A HIGH to LOW transition of the SD line while the clock (SC)
is HIGH defines a START condition.
Stop data transfer (3)
A LOW to HIGH transition of the SD line while the clock (SC)
is HIGH defines a STOP condition.
Data valid (4)
The state of the data line represents valid data when, after
START condition, the data line is stable for the duration of the
HIGH period of the clock signal.
Acknowledge
All address and data words are serially transmitted to and
from the device in eight-bit words. The receiving device
returns a zero on the data line during the ninth clock cycle to
acknowledge word receipt.
Figure 47.
MCL Bus Protocol 2
SSI Interrupt
The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e.,
transmit buffer empty or receive buffer full) at the end of an SSI data telegram or on the
falling edge of the SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is per-
formed by the Interrupt Function control bit (IFN). The SSI interrupt is usually used to
synchronize the software control of the SSI and inform the controller of the present SSI
status. Port 4 interrupts can be used together with the SSI or, if the SSI itself is not
required, as additional external interrupt sources. In either case this interrupt is capable
of waking the controller out of sleep mode.
To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and
the Interrupt Function (IFN) while Port 4 interrupts are enabled by setting appropriate
control bits in P4CR register.
(2)
(1)
(4)
(4)
(3)
(1)
Start
condition
Data
valid
Data
change
Data
valid
Stop
condition
SC
SD
SC
SD
Start
1
n
8
9
1st Bit
8th Bit
ACK
Stop