參數(shù)資料
型號： AT32AP7002-CTUT
廠商： Atmel
文件頁數(shù)： 75/83頁
文件大小： 0K
描述： IC MCU 32BIT AVR32 196-CBGA
產(chǎn)品培訓模塊： MCU Product Line Introduction
標準包裝： 945
系列： AVR®32 AP7
核心處理器： AVR
芯體尺寸： 32-位
速度： 150MHz
連通性： EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB
外圍設備： AC'97，DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 85
程序存儲器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： D/A 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 196-CBGA
包裝： 托盤
配用： ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATNGW100-ND - KIT AVR32 NETWORK GATEWAY
ATSTK1000-ND - KIT STARTER FOR AVR32AP7000
2011 Microchip Technology Inc.
DS70118J-page 69
dsPIC30F2010
11.2
Input Capture Operation During
Sleep and Idle Modes
An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU Idle or
Sleep mode.
Independent of the timer being enabled, the input
capture module will wake-up from the CPU Sleep or
Idle
mode
when
a
capture
event
occurs,
if
ICM<2:0> = 111 and the interrupt enable bit is
asserted. The same wake-up can generate an inter-
rupt, if the conditions for processing the interrupt have
been satisfied. The wake-up feature is useful as a
method of adding extra external pin interrupts.
11.2.1
INPUT CAPTURE IN CPU SLEEP
MODE
CPU Sleep mode allows input capture module opera-
tion with reduced functionality. In the CPU Sleep
mode, the ICI<1:0> bits are not applicable, and the
input capture module can only function as an external
interrupt source.
The capture module must be configured for interrupt
only on the rising edge (ICM<2:0> = 111), in order for
the input capture module to be used while the device
is in Sleep mode. The prescale settings of 4:1 or 16:1
are not applicable in this mode.
11.2.2
INPUT CAPTURE IN CPU IDLE
MODE
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the interrupt
mode selected by the ICI<1:0> bits are applicable, as
well as the 4:1 and 16:1 capture prescale settings,
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover, the
ICSIDL bit must be asserted to a logic ‘0’.
If
the
input
capture
module
is
defined
as
ICM<2:0> = 111 in CPU Idle mode, the input capture
pin will serve only as an external interrupt pin.
11.3
Input Capture Interrupts
The input capture channels have the ability to generate
an interrupt, based upon the selected number of cap-
ture events. The selection number is set by control bits
ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx status register.
Enabling an interrupt is accomplished via the respec-
tive capture channel interrupt enable (ICxIE) bit. The
capture
interrupt
enable
bit
is
located
in
the
corresponding IEC Control register.
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