參數(shù)資料
型號: AT32AP7002-CTUT
廠商: Atmel
文件頁數(shù): 13/83頁
文件大?。?/td> 0K
描述: IC MCU 32BIT AVR32 196-CBGA
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 945
系列: AVR®32 AP7
核心處理器: AVR
芯體尺寸: 32-位
速度: 150MHz
連通性: EBI/EMI,I²C,MMC,PS2,SPI,SSC,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: D/A 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 196-CBGA
包裝: 托盤
配用: ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATNGW100-ND - KIT AVR32 NETWORK GATEWAY
ATSTK1000-ND - KIT STARTER FOR AVR32AP7000
20
32054F–AVR32–09/09
AT32AP7002
6.2.5
Caches and write buffer
AVR32 AP implements 16K data and 16K instruction caches. The caches are 4-way set asso-
ciative. Each cache has a 32-bit System Bus master interface connecting it to the bus. The
instruction cache has a 32-bit interface to the fetch pipeline stage, and the data cache has a 64-
bit interface to the load-store pipeline. The caches use a least recently used allocate-on-read-
miss replacement policy. The caches are virtually tagged, physically indexed, avoiding the need
to flush them on task switch.
The caches provide locking on a per-line basis, allowing code and data to be permanently
locked in the caches for timing-critical code. The data cache also allows prefetching of data
using the pref instruction.
Accesses to the instruction and data caches are tagged as cacheable or uncacheable on a per-
page basis by the MMU. Data cache writes are tagged as write-through or writeback on a per-
page basis by the MMU.
The data cache has a 32-byte combining write buffer, to avoid stalling the CPU when writing to
external memory. Writes are tagged as bufferable or unbufferable on a per-page basis by the
MMU. Bufferable writes to sequential addresses are placed in the buffer, allowing for example a
sequence of byte writes from the CPU to be combined into word transfers on the bus. A sync
instruction is provided to explicitly flush the write buffer.
6.2.6
Unaligned reference handling
AVR32 AP has hardware support for performing unaligned memory accesses. This will reduce
the memory footprint needed by some applications, as well as speed up other applications oper-
ating on unaligned data.
AVR32 AP is able to perform certain word-sized load and store instructions of any alignment,
and word-aligned st.d and ld.d. Any other unaligned memory access will cause an MMU address
exception. All coprocessor memory access instructions require word-aligned pointers. Double-
word-sized accesses with word-aligned pointers will automatically be performed as two word-
sized accesses.
The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses. Accessing an unaligned address may require several
clock cycles, refer to the AVR32 AP Technical Reference Manual for details.
Table 6-1.
Instructions with unaligned reference support
Instruction
Supported alignment
ld.w
Any
st.w
Any
lddsp
Any
lddpc
Any
stdsp
Any
ld.d
Word
st.d
Word
All coprocessor memory access instruction
Word
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