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| 型號(hào)： | AT32AP7002-CTUT |
| 廠商： | Atmel |
| 文件頁數(shù)： | 74/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT AVR32 196-CBGA |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction |
| 標(biāo)準(zhǔn)包裝： | 945 |
| 系列： | AVR®32 AP7 |
| 核心處理器： | AVR |
| 芯體尺寸： | 32-位 |
| 速度： | 150MHz |
| 連通性： | EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB |
| 外圍設(shè)備： | AC'97，DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 85 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | D/A 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 196-CBGA |
| 包裝： | 托盤 |
| 配用： | ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR ATNGW100-ND - KIT AVR32 NETWORK GATEWAY ATSTK1000-ND - KIT STARTER FOR AVR32AP7000 |
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dsPIC30F2010
DS70118J-page 68
2011 Microchip Technology Inc.
11.1
Simple Capture Event Mode
The simple capture events in the dsPIC30F product
family are:
Capture every falling edge
Capture every rising edge
Capture every 4th rising edge
Capture every 16th rising edge
Capture every rising and falling edge
These simple Input Capture modes are configured by
setting the appropriate bits ICM<2:0> (ICxCON<2:0>).
11.1.1
CAPTURE PRESCALER
There are four input capture prescaler settings, speci-
fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter will
be cleared. In addition, any Reset will clear the
prescaler counter.
11.1.2
CAPTURE BUFFER OPERATION
Each capture channel has an associated FIFO buffer,
which is four 16-bit words deep. There are two status
flags, which provide status on the FIFO buffer:
ICBNE – Input Capture Buffer Not Empty
ICOV – Input Capture Overflow
The ICBFNE will be set on the first input capture event
and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
ICOV bit will be set to a logic ‘1’. The fifth capture event
is lost and is not stored in the FIFO. No additional
events will be captured until all four events have been
read from the buffer.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
11.1.3
TIMER2 AND TIMER3 SELECTION
MODE
The input capture module consists of up to eight input
capture channels. Each channel can select between
one of two timers for the time base, Timer2 or Timer3.
Selection of the timer resource is accomplished
through SFR bit ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
11.1.4
HALL SENSOR MODE
When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the fol-
lowing operations are performed by the input capture
logic:
The input capture interrupt flag is set on every
edge, rising and falling.
The interrupt on Capture mode setting bits,
ICI<1:0>, is ignored, since every capture
generates an interrupt.
A capture overflow condition is not generated in
this mode.
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