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| 型號： | AT32AP7002-CTUT |
| 廠商： | Atmel |
| 文件頁數(shù)： | 58/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT AVR32 196-CBGA |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction |
| 標準包裝： | 945 |
| 系列： | AVR®32 AP7 |
| 核心處理器： | AVR |
| 芯體尺寸： | 32-位 |
| 速度： | 150MHz |
| 連通性： | EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB |
| 外圍設(shè)備： | AC'97，DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 85 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | D/A 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 196-CBGA |
| 包裝： | 托盤 |
| 配用： | ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR ATNGW100-ND - KIT AVR32 NETWORK GATEWAY ATSTK1000-ND - KIT STARTER FOR AVR32AP7000 |
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2011 Microchip Technology Inc.
DS70118J-page 53
dsPIC30F2010
8.0
I/O PORTS
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
8.1
Parallel I/O (PIO) Ports
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with the operation of the port pin. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins, and writes to the
port pins, write the latch (LATx).
Any bit and its associated data and control registers
that are not valid for a particular device will be disabled.
That means the corresponding LATx and TRISx
registers and the port pin will read as zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
A parallel I/O (PIO) port that shares a pin with a periph-
eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 8-1 shows how ports are shared
with other peripherals, and the associated I/O cell (pad)
to which they are connected. Table 8-1 shows the
formats of the registers for the shared ports, PORTB
through PORTF.
FIGURE 8-1:
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Q
D
CK
WR LAT +
TRIS Latch
I/O Pad
WR Port
Data Bus
Q
D
CK
Data Latch
Read LAT
Read Port
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data
Peripheral Input Data
I/O Cell
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Input Data
Peripheral Module Enable
Output Enable
Output Data
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