參數(shù)資料
型號(hào)： AT32AP7002-CTUT
廠商： Atmel
文件頁(yè)數(shù)： 70/83頁(yè)
文件大小： 0K
描述： IC MCU 32BIT AVR32 196-CBGA
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 945
系列： AVR®32 AP7
核心處理器： AVR
芯體尺寸： 32-位
速度： 150MHz
連通性： EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 85
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： D/A 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 196-CBGA
包裝： 托盤
配用： ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATNGW100-ND - KIT AVR32 NETWORK GATEWAY
ATSTK1000-ND - KIT STARTER FOR AVR32AP7000
dsPIC30F2010
DS70118J-page 64
2011 Microchip Technology Inc.
10.1
Timer Gate Operation
The 32-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input sig-
nal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
The falling edge of the external signal terminates the
count operation, but does not reset the timer. The user
must reset the timer in order to start counting from zero.
10.2
ADC Event Trigger
When a match occurs between the 32-bit timer (TMR3/
TMR2) and the 32-bit combined period register (PR3/
PR2), a special ADC trigger event signal is generated
by Timer3.
10.3
Timer Prescaler
The input clock (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler oper-
ation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
A write to the TMR2/TMR3 register
Clearing either of the TON (T2CON<15> or
T3CON<15>) bits to ‘0’
Device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset, since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
10.4
Timer Operation During Sleep
Mode
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
10.5
Timer Interrupt
The 32-bit timer module can generate an interrupt on
period match, or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external “gate” signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt will be gener-
ated if enabled. In this mode, the T3IF interrupt flag is
used as the source of the interrupt. The T3IF bit must
be cleared in software.
Enabling
an
interrupt
is
accomplished
via
the
respective timer interrupt enable bit, T3IE (IEC0<7>).
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