參數(shù)資料
型號(hào)： AT32AP7002-CTUT
廠商： Atmel
文件頁(yè)數(shù)： 35/83頁(yè)
文件大小： 0K
描述： IC MCU 32BIT AVR32 196-CBGA
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 945
系列： AVR®32 AP7
核心處理器： AVR
芯體尺寸： 32-位
速度： 150MHz
連通性： EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 85
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： D/A 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 196-CBGA
包裝： 托盤
配用： ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATNGW100-ND - KIT AVR32 NETWORK GATEWAY
ATSTK1000-ND - KIT STARTER FOR AVR32AP7000
dsPIC30F2010
DS70118J-page 32
2011 Microchip Technology Inc.
4.1.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (i.e., the
Addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or 5-bit literal. The result
location can be either a W register or an address
location.
The
following
Addressing
modes
are
supported by MCU instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
5-bit or 10-bit Literal
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, Move and Accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
In summary, the following Addressing modes are
supported by Move and Accumulator instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
4.1.4
MAC
INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC
and MSC), also
referred to as MAC instructions, utilize a simplified set of
Addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
In summary, the following Addressing modes are
supported by the MAC class of instructions:
Register Indirect
Register Indirect Post-modified by 2
Register Indirect Post-modified by 4
Register Indirect Post-modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Besides the various Addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
Note:
Not
all
instructions
support
all
the
Addressing modes given above. Individ-
ual instructions may support different
subsets of these Addressing modes.
Note:
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared
between
both
source
and
destination (but typically only used by
one).
Note:
Not
all
instructions
support
all
the
Addressing modes given above. Individ-
ual instructions may support different
subsets of these Addressing modes.
Note:
Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
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