參數(shù)資料
型號(hào)： AS4LC256K16EO
廠商： Alliance Semiconductor Corporation
英文描述： 3.3V 256K×16 CMOS DRAM (EDO)(3.3V 256K×16 CMOS動(dòng)態(tài)RAM（擴(kuò)展數(shù)據(jù)總線）)
中文描述： 3.3 256K × 16的CMOS的DRAM（江戶）（3.3 256K × 16的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器（擴(kuò)展數(shù)據(jù)總線））
文件頁(yè)數(shù)： 2/25頁(yè)
文件大?。?/td> 528K
代理商： AS4LC256K16EO
AS4LC256K16EO
2/1/01;
V.1.0
Alliance Semiconductor
P. 2 of 25
Functional description
The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as
262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative
design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.
The AS4LC256K16EO features a high speed page mode operation in which high speed read, write and read-write are
performed on any of the 512
×
16 bits defined by the column address. The asynchronous column address uses an extremely
short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fast
CAS
to output access time eases system design.
Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the
following:
RAS-only refresh cycles
Hidden refresh cycles
CAS-before-RAS refresh cycles
Normal read or write cycles
Self refresh cycles
The AS4LC256K16EO is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely
available automated testing and insertion equipment. System level features include single power supply of 3.3V
±
0.3V
tolerance and direct interface with TTL logic families.
Logic block diagram
Recommended operating conditions
Parameter
(T
a
= 0°C to +70°C)
Max
Symbol
Min
Typ
Unit
Supply voltage
V
CC
GND
3.0
3.3
3.6
V
0.0
0.0
0.0
V
Input voltage
V
IH
V
IL
2.0
–
V
CC
+ 1
0.8
V
–1.0
–
V
512×512×16
ARRAY
(4,194,304)
SENSE AMP
A0
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
GND
A
R
COLUMN DECODER
RAS CLOCK
GENERATOR
SUBSTRATE
BIAS
GENERATOR
DATA
I/O
BUFFER
OE
RAS
UCAS
WE CLOCK
GENERATOR
WE
LCAS
I/O0 to I/O15
CAS CLOCK
GENERATOR
相關(guān)PDF資料
PDF描述
AS4LC4M16S0 3.3V 4M × 16 CMOS Synchronous DRAM(3.3V 4M × 16 CMOS同步動(dòng)態(tài)RAM)
AS4LC4M16S0-75TC 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
AS4LC4M16S0-8TC 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
AS4LC8M8S0 3.3V 8M × 8 CMOS Synchronous DRAM(3.3V 8M × 8 CMOS同步動(dòng)態(tài)RAM)
AS4LC4M16S0-10FTC 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS4LC256K16EO-35 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO)
AS4LC256K16EO-35TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO)
AS4LC256K16EO-45TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO)
AS4LC256K16EO-60JC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO)
AS4LC256K16EO-60TC 制造商:ALLIANCE 功能描述: 制造商:Alliance Memory Inc 功能描述:
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