參數(shù)資料
型號： AMD ATHLON
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻)
中文描述： 32三維多媒體性能和數(shù)字視頻比特微處理器（32位微處理器帶三維多媒體性能和數(shù)字視頻）
文件頁數(shù)： 74/106頁
文件大?。?/td> 1740K
代理商： AMD ATHLON
60
Interface Signals
Chapter 10
AMD Athlon
Processor Data Sheet
21016G/0
—
December 1999
Preliminary Information
SFILLVAL#
I
OD
V
CCCORE
1
SFILLVAL# validates a data transfer to the processor. The system
may tie this pin to the asserted state (validating all fills). The
processor samples SFILLVAL# at the first or second data beat.
SMI# is an input that causes the processor to enter the system
management mode.
SMI#
I
OD
V
CCCORE
OD
V
CCCORE
1
STPCLK#
I
1
STPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
SYSCLK and SYSCLK# are differential input clock signals
provided to the processor
’
s PLL from a system-clock generator.
VCC2SEL is an output to the system that indicates the required
core voltage for the L2 SRAM. High=2.5V, Low=3.3V.
The VID[3:0] signals are outputs to the motherboard that
indicate the required V
CCCORE
voltage for the processor.
SYSCLK
SYSCLK#
I
2
VCC2SEL
O
OD
V
CCCORE
OD
V
CCCORE
1
VID[3:0]
O
4
Table 21. AMD Athlon
System Bus and Legacy Interface Signals (continued)
Signal Name
Type
Level
Number
of Pins
Description
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