參數(shù)資料
型號(hào)： AMD ATHLON
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻)
中文描述： 32三維多媒體性能和數(shù)字視頻比特微處理器（32位微處理器帶三維多媒體性能和數(shù)字視頻）
文件頁(yè)數(shù)： 26/106頁(yè)
文件大小： 1740K
代理商： AMD ATHLON
12
Power Management
Chapter 4
AMD Athlon
Processor Data Sheet
21016G/0
—
December 1999
Preliminary Information
The following sections describe each of the low-power states.
Note:
In all power management states, the system must not
disable the system clock (SYSCLK/SYSCLK#) to the
processor.
Full-On
The Full-on or normal state refers to the default power state
and means that all functional units are operating at full
processor clock speed.
Halt State
When the AMD Athlon processor executes the HLT instruction,
the processor issues a Halt special cycle to the system bus. The
phase-lock loop (PLL) continues to run, enabling the processor
to monitor bus activity and provide a quick resume from the
Halt state. The processor may enter a lower power state.
The Halt state is exited when the processor samples INIT#,
INTR (if interrupts are enabled), NMI, RESET#, or SMI#.
Stop Grant and Sleep
States
After recognizing the assertion of STPCLK#, the AMD Athlon
processor completes all pending and in-progress bus cycles and
acknowledges the STPCLK# assertion by issuing a Stop Grant
special bus cycle to the system bus. The processor may enter a
lower power state.
From a software standpoint, the Sleep/Stop Grant state is
entered by reading the PLVL registers located in an
ACPI-compliant peripheral bus controller. The difference
between the Stop Grant state and the Sleep state is determined
by which PLVL register software reads from the peripheral bus
controller. If the software reads the PLVL_2 register, the
processor enters the Stop Grant state. In this state, probes are
allowed, as shown in Figure 3 on page 11. If the software reads
the PLVL_3 register, the processor enters the Sleep state, where
probes are not allowed. This action is accomplished by disabling
snoops within an ACPI-compliant system controller.
The Sleep/Stop Grant state is exited upon the deassertion of
STPCLK# or the assertion of RESET#. After the processor
enters the Full-on state, it resumes execution at the instruction
boundary where STPCLK# was initially recognized.
The processor latches INIT#, INTR (if interrupts are enabled),
NMI, and SMI#, if they are asserted during the Stop Grant or
Sleep state. However, the processor does not exit this state until
the deassertion of STPCLK#. When STPCLK# is deasserted,
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