參數(shù)資料
型號(hào)： AMD ATHLON
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻)
中文描述： 32三維多媒體性能和數(shù)字視頻比特微處理器（32位微處理器帶三維多媒體性能和數(shù)字視頻）
文件頁(yè)數(shù)： 73/106頁(yè)
文件大小： 1740K
代理商： AMD ATHLON
Chapter 10
Interface Signals
59
21016G/0
—
December 1999
AMD Athlon
Processor Data Sheet
Preliminary Information
PICD[1:0]#
I
OD
V
CCCORE
2
PICD[1:0]# are bidirectional signals that are used by the APIC
bus, and must be connected to all APIC data pins on all devices
of the APIC bus.
PROCRDY is an output to the system and is used for power
management and source-synchronous clock initialization at
reset.
PWROK is an input from the system indicating that the core
power is within specified limits.
PROCRDY
O
OD
V
CCCORE
1
PWROK
I
OD
V
CCCORE
OD
V
CCCORE
OD
V
CCCORE
OD
V
CCCORE
1
RESET#
I
1
RESET# is an input from the system that initializes and resets the
processor and invalidates cache blocks.
SADDIN[14:2]#
I
13
SADDIN[14:2]# is the unidirectional system probe and data
movement command channel from the system.
SADDINCLK#
I
1
SADDINCLK# is the single-ended source-synchronous clock for
SADDIN[14:2]# and is driven by the system.
SADDOUT[14:2]# is the unidirectional processor request channel
to the system. It is used to transfer processor requests or probe
responses to the system.
SADDOUTCLK# is the single-ended source-synchronous clock
for SADDOUT[14:2]# driven by the processor.
SADDOUT[14:2]#
O
OD
V
CCCORE
13
SADDOUTCLK#
O
OD
V
CCCORE
OD
V
CCCORE
OD
V
CCCORE
1
SCHECK[7:0]#
I/O
8
SCHECK[7:0]# contain the ECC bits for data transfers on
SDATA[63:0]#.
SDATA[63:0]#
I/O
64
SDATA[63:0]# is the bidirectional channel between the processor
and system for data movement.
SDATAINCLK[3:0]# is the single-ended forwarded clock driven
by the system to transfer data on SDATA[63:0]#. Each 16-bit data
word is skewed-aligned with this clock.
SDATAINVAL# is driven by the system to pace the data into the
processor. SDATAINVAL# can be used to introduce an arbitrary
number of cycles between octawords into the processor.
SDATAOUTCLK[3:0]# is the single-ended source-synchronous
clock driven by the processor to transfer data on SDATA[63:0]#.
Each 16-bit data word on SDATA[63:0]# is skewed-aligned with
this clock.
SDATAOUTVAL# is driven by the system to pace the data from
the processor. SDATAOUTVAL# can be used to introduce an
arbitrary number of cycles between quadwords from the
processor.
SDATAINCLK[3:0]#
I
OD
V
CCCORE
4
SDATAINVAL#
I
OD
V
CCCORE
1
SDATAOUTCLK[3:0]#
O
OD
V
CCCORE
4
SDATAOUTVAL#
I
OD
V
CCCORE
1
Table 21. AMD Athlon
System Bus and Legacy Interface Signals (continued)
Signal Name
Type
Level
Number
of Pins
Description
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