參數(shù)資料
型號： AMD ATHLON
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻)
中文描述： 32三維多媒體性能和數(shù)字視頻比特微處理器（32位微處理器帶三維多媒體性能和數(shù)字視頻）
文件頁數(shù)： 40/106頁
文件大?。?/td> 1740K
代理商： AMD ATHLON
26
Electrical Data
Chapter 6
AMD Athlon
Processor Data Sheet
21016G/0
—
December 1999
Preliminary Information
6.4
Frequency Identification
The AMD Athlon processor provides four frequency ID signals
(FID[3:0]) to the system controller to indicate the SYSCLK
multiplier at which the processor core operates. This
mechanism is automatic, using the system controller and the
BIOS without jumpers on the motherboard to set the operating
frequency of the AMD Athlon.
6.5
Decoupling
See the
AMD Athlon
Processor Voltage Regulation Design
Application Note
, order# 22651, or contact your local AMD office
for information about the decoupling required on the
motherboard for use with the AMD Athlon processor.
6.6
Termination
Table 8 lists the layout and termination for Slot-A signals and
clocks.
For additional information concerning termination design
guidelines for AMD Athlon processor-based systems, contact
your local AMD representative to obtain detailed
documentation available under a non-disclosure agreement.
Table 8.
Signal and Clock Layout and Termination Requirements
Group/Name
Termination Requirements
SYSCLK, SYSCLK#
Differential clock inputs to the system controller (Northbridge) and Slot-A.
Point-to-point system clocks driven by the central system clock generator. See
“
SYSCLK, SYSCLK#
”
on page 27.
SDATA0, SDATA1, SDATA2, SDATA3,
SADDIN, SADDOUT
*
CLKFWDRST, CONNECT, PROCRDY
PICCLK
PICD[1:0]
68 ohm pullup resistors must be kept with 1
”
of Northbridge. See
“
OD
Termination
”
on page 27.
These signals must be pulled to 2.5 V on the motherboard using a 330-ohm
resistor to Vcc3 and a 1.0-kohm resistor to Vss.
NMI, INTR, SMI#, INIT#, A20M#,
IGNNE#, STPCLK#, CPURESET#
Route to minimum length where possible. HSTL-like inputs. Point-to-point
signals driven by the peripheral bus controller (Southbridge) to the Slot-A
connector. These signals are pulled to VccCore on the Slot-A card and do not
require termination on the motherboard.
Notes:
*
See Table 6, “Source-Synchronous Clock Signal Groups,” on page 24
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