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參數(shù)資料
| 型號(hào)： | AMD ATHLON |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻) |
| 中文描述： | 32三維多媒體性能和數(shù)字視頻比特微處理器（32位微處理器帶三維多媒體性能和數(shù)字視頻） |
| 文件頁數(shù)： | 41/106頁 |
| 文件大?。?/td> | 1740K |
| 代理商： | AMD ATHLON |
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Chapter 6
Electrical Data
27
21016G/0
—
December 1999
AMD Athlon
Processor Data Sheet
Preliminary Information
OD Termination
Both the processor and Northbridge use HSTL-like open-drain
outputs and HSTL-like inputs. Therefore, the bus signals must
be terminated both at the source and the destination with 68
pullup resistors to VccCore. Pullups at the processor are
located on the processor module and need not be considered
during motherboard layout. Consequently, the only
terminations required on the motherboard are the pullup
resistors at the Northbridge. These pullup termination resistors
must be located 1 inch from the Northbridge.
For systems that do not support ECC, SCHECK[7:0]# should be
tied to VccCore with a 68-ohm pullup, with minimal routing
where possible.
CLKFWD Signal
Groups
The termination scheme for all clock forward signals, both
signal and clock, involves having each end terminated by a
68-ohm pullup resistor located 1 inch from each device. Pullups
at the processor are located on the processor module and need
not be considered during motherboard layout.
Note:
The data bus, SDATA[63:0], drives in both directions and,
therefore, must have a unidirectional clock for each data
group travelling each way.
SYSCLK, SYSCLK#
Each of the two SYSCLK pairs from the clock generator to the
processor, SYSCLK and SYSCLK# (true and complimentary),
located a maximum distance of 0.5 inch from the clock
generator and parallel terminated at the end with a 68-ohm
resistor to VccCore. Parallel termination occurs on the
processor module and need not be considered during
motherboard layout.
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