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參數(shù)資料
| 型號(hào)： | AMD ATHLON |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻) |
| 中文描述： | 32三維多媒體性能和數(shù)字視頻比特微處理器（32位微處理器帶三維多媒體性能和數(shù)字視頻） |
| 文件頁數(shù)： | 27/106頁 |
| 文件大小： | 1740K |
| 代理商： | AMD ATHLON |
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Chapter 4
Power Management
13
21016G/0
—
December 1999
AMD Athlon
Processor Data Sheet
Preliminary Information
any pending interrupts are recognized after returning to the
Normal state.
If RESET# is sampled asserted during the Stop Grant or Sleep
state, the processor immediately returns to the Full-on state
and the reset process begins.
Probe State
The Probe state is entered when the system requires the
processor to service a probe. When in the Probe state, the
processor responds to a probe cycle in the same manner as
when it is in the Full-on state.
When the probe has been serviced, the processor returns to the
same state as when it entered the Probe state.
4.2
Connection and Disconnection Protocol
The AMD Athlon processor enhances power savings in each of
the power management states when the system logic
disconnects the processor from the system bus and slows down
the internal clocks. Entering the lowest power state is
accomplished with a connection protocol between the processor
and system logic. The system can initiate a bus disconnection
upon the receipt of a Stop Grant special cycle. If required by the
system, the processor disconnects from the system bus and
slows down its internal clocks before entering the Stop Grant or
Sleep state. If the system requires the processor to service a
probe while it is in the Stop Grant state, it must first request
that the processor increase its clocks to full speed and
reconnect to the system bus. Table 3 on page 14 describes the
AMD Athlon processor power states using the connection
protocol as described on page 14.
AMD Athlon system bus connections and disconnections are
controlled by an enable bit within the system controller.
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