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參數(shù)資料
| 型號： | AMD ATHLON |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻) |
| 中文描述： | 32三維多媒體性能和數(shù)字視頻比特微處理器（32位微處理器帶三維多媒體性能和數(shù)字視頻） |
| 文件頁數(shù)： | 71/106頁 |
| 文件大?。?/td> | 1740K |
| 代理商： | AMD ATHLON |
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Chapter 10
Interface Signals
57
21016G/0
—
December 1999
AMD Athlon
Processor Data Sheet
Preliminary Information
10
Interface Signals
10.1
Overview
The AMD Athlon system bus architecture is designed to deliver
unprecedented data movement bandwidth for next-generation
x86 platforms, as well as the high performance required by
enterprise-class application software. The system bus
architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 72-bit bidirectional data channel,
including 8-bit error code correction [ECC] protection),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use a HSTL-like,
low-voltage swing signaling technology contained within the
Slot A mechanical connector, which is mechanically compatible
with the industry-standard SC242 connector.
10.2
Signaling Technology
The AMD Athlon processor Model 2 uses the same signaling
technology as the AMD Athlon processor Model 1. For
information about the bus signaling technology for the
AMD Athlon processor Model 2, see Chapter 2,
“
Interface
Signals
”
on page 5.
10.3
AMD Athlon
System Bus Signals
Table 21 on page 58 shows the AMD Athlon system bus signals
and legacy interface signals. The difference between the
AMD Athlon Model 2 and Model 1 processors with respect to
legacy interface signals is the addition of the industry-standard
APIC signals, PICCLK and PICD[1:0]#. Table 20 on page 58
shows the pin-type definitions used in the
Type
column of Table
21.
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