參數(shù)資料
型號： AMD ATHLON
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻)
中文描述： 32三維多媒體性能和數(shù)字視頻比特微處理器（32位微處理器帶三維多媒體性能和數(shù)字視頻）
文件頁數(shù)： 72/106頁
文件大?。?/td> 1740K
代理商： AMD ATHLON
58
Interface Signals
Chapter 10
AMD Athlon
Processor Data Sheet
21016G/0
—
December 1999
Preliminary Information
Table 20. Pin-Type Definitions
Mnemonic
I
O
I/O
Definition
Standard input pin to the processor
Standard output pin from the processor
Bidirectional, three-state input/output pin
Open-drain structure that allows multiple devices to share the
pin in a wired-OR configuration
Push/Pull structure driven by a single source
AMD Athlon processor core voltage
OD
PP
V
CCCORE
Table 21. AMD Athlon
System Bus and Legacy Interface Signals
Signal Name
Type
Level
Number
of Pins
Description
A20M#
I
OD
V
CCCORE
OD
V
CCCORE
OD
V
CCCORE
PP
V
CCCORE
1
A20M# is an input from the system used to simulate address
wrapping around in the 20-bit 8086.
CLKFWDRST
I
1
CLKFWDRST resets clock-forward circuitry for both the system
and processor.
CONNECT
I
1
CONNECT is an input from the system used for power
management and clock-forward initialization at reset.
COREFB+
COREFB
–
O
2
COREFB+ and COREFB
–
are outputs to the system that provide
AMD Athlon processor core voltage feedback to the system.
FERR
O
OD
V
CCCORE
1
FERR is an output to the system that is asserted for any
unmasked numerical exception independent of the NE bit in
CR0.
The FID[3:0] signals are outputs to the system that report the
multiplier used on the system clock (SYSCLK) producing the
AMD Athlon processor core clock.
IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# is an input from the system that resets the integer registers
without affecting the floating-point registers or the internal
caches. Execution starts at 0FFFF FFF0h.
INTR is an input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the 8-bit
interrupt vector and starts execution at that location.
NMI is an input from the system that causes a non-maskable
interrupt.
FID[3:0]
O
OD
V
CCCORE
4
IGNNE#
I
OD
V
CCCORE
1
INIT#
I
OD
V
CCCORE
1
INTR
I
OD
V
CCCORE
1
NMI
I
OD
V
CCCORE
PP
V
CCCORE
1
PICCLK
I
1
PICCLK is an input clock that is required for operation of the
APIC bus.
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