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| 型號： | AM79C940JCW |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁數(shù)： | 91/122頁 |
| 文件大小： | 914K |
| 代理商： | AM79C940JCW |
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AMD
91
Am79C940
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified (continued)
Parameter
Symbol
Parameter Description
Test Conditions
V
RXDTH
RXD Switching Threshold
(Note 4)
V
TXH
TXD
±
and TXP
±
Output
HIGH Voltage
DV
SS
= 0 V
V
TXL
TXD
±
and TXP
±
Output
LOW Voltage
DV
DD
= +5 V
V
TXI
TXD
±
and TXP
±
Differential Output
Voltage Imbalance
V
TXOFF
TXD
±
and TXP
±
Idle
Output Voltage
DV
DD
= +5 V
R
TX
TXD
±
Differential Driver
Output Impedance
(Note 8)
TXP
±
Differential Driver
Output Impedance
(Note 8)
Min
–35
Max
35
Unit
mV
DV
DD
– 0.6
DV
DD
V
DV
SS
DV
SS
+ 0.6
V
–40
+40
mV
40
mV
40
80
Notes:
1. V
OH
does not apply to open-drain output pins.
2. I
IL1
and I
IL2
applies to all input only pins except DI
±
, CI
±
, and XTAL1.
I
IL1
= ADD4–0,
BE
1–0,
CS
,
EAM/R
,
FDS
,
RESET
, RXDAT, R/
W
, SCLK.
I
IL2
=
TC
, TDI, TCK, TMS.
3. Specified for input only pins with internal pull-ups:
TC
, TDI, TCK, TMS.
4. I
OZ
applies to all three-state output pins and bi-directional pins.
5. Test not implemented to data sheet specification.
6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.
7. During the activation of
SLEEP
:
–
The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR,
DTV
,
TDTREQ
,
RDTREQ
,
NTR
and TDO.
–
The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled:
DBUS15–0,
EOF
, SRDCLK, RXCRS, RXDAT, CLSN,
TXEN
, STDCLK and TXDAT+.
–
The following input pin has its internal pull-up and TTL level translator disabled:
TC
.
–
The following input pins have their internal TTL level translators disabled and do not have internal pull-ups:
CS
,
FDS
,
R/
W
, ADD4–0, SCLK,
BE
0,
BE
1 and
EAM/R
.
–
The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+
and DO.
–
The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI.
–
AWAKE and RWAKE are reset to zero. I
DDSLEEP
,
with either AWAKE set or RWAKE set, will be much higher and its value
remains to be determined.
8. Parameter not tested.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C940JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940JI/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940KC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE) |
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