參數(shù)資料
型號(hào): AM79C940JCW
廠商: Advanced Micro Devices, Inc.
英文描述: Media Access Controller for Ethernet (MACE)
中文描述: 媒體訪問控制器(MACE發(fā)生以太網(wǎng))
文件頁數(shù): 77/122頁
文件大?。?/td> 914K
代理商: AM79C940JCW
AMD
77
Am79C940
Programmer’s Register Model (continued)
Addr
Mnemonic
9
IMR
Interrupt Mask Register
80
40
20
10
08
04
02
01
10
PR
Poll Register
80
40
20
11
BIUCC
Bus Interface Unit Configuration Control
80
40
30
Contents
R/W
JABM
BABLM
CERRM
RCVCCOM
RNTPCOM
MPCOM
RCVINTM
XMTINTM
Jabber Error Mask
Babble Error Mask
Collision Error Mask
Receive Collision Count Overflow Mask
Runt Packet Count Overflow Mask
Missed Packet Count Overflow Mask
Receive Interrupt Mask
Transmit Interrupt Mask
XMTSV
TDTREQ
RDTREQ
Transmit Status Valid
Transmit Data Transfer Request
Receive Data Transfer Request
RO
BSWP
XMTSP—Transmit Start Point (2 bits)
00
Transmit after 4 bytes have been loaded
01
Transmit after 16 bytes have been loaded
10
Transmit after 64 bytes have been loaded
11
Transmit after 112 bytes have been loaded
SWRST
Software Reset
FIFO Configuration Control
C0
XMTFW
Transmit FIFO Watermark (2 bits)
00
Assert TDTREQ after 8 write cycles can be made
01
Assert TDTREQ after 16 write cycles can be made
10
Assert TDTREQ after 32 write cycles can be made
11
XX
30
RCVFW
Receive FIFO Watermark (2 bits)
00
Assert RDTREQ after 16 bytes are present
01
Assert RDTREQ after 32 bytes are present
10
Assert RDTREQ after 64 bytes are present
11
XX
08
XMTFWU
Transmit FIFO Watermark Update—loads XMTFW bits
04
RCVFWU
Receive FIFO Watermark Update—loads RCVFW bits
02
XMTBRST
Select Transmit Burst mode
01
RCVBRST
Select Receive Burst mode
Media Access Control (MAC) Configuration Control
80
PROM
Promiscuous mode
40
DXMT2PD
Disable Transmit Two Part Deferral
20
EMBA
Enable Modified Back-off Algorithm
10
08
DRCVPA
Disable Receive Physical Address
04
DRCVBC
Disable Receive Broadcast
02
ENXMT
Enable Transmit
01
ENRCV
Enable Receive
Byte Swap
01
12
FIFOCC
13
MACCC
R/W
R/W
R/W
R/W
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